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參數(shù)資料
| 型號： | M40Z111MH6TR |
| 廠商： | 意法半導體 |
| 英文描述： | 5V OR 3V NVRAM SUPERVISOR FOR UP TO TWO LPSRAMs |
| 中文描述： | 5V或3V NVRAM中的主管，直到兩名LPSRAMs |
| 文件頁數(shù)： | 9/15頁 |
| 文件大小： | 114K |
| 代理商： | M40Z111MH6TR |
9/15
M40Z111, M40Z111W
Table 6. Power Down/Up AC Characteristics
Note: 1. Valid for Ambient Operating Temperature: T
A
= –40 to 85°C; V
CC
= 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
2. V
PFD
(max) to V
PFD
(min) fall time of less than tF may result in deselection/write protection not occurring until 200 μs after V
CC
passes V
PFD
(min).
3. V
PFD
(min) to V
SS
fall time of less than tFB may cause corruption of RAM data.
4. t
ER
(min) = 20ms for Industrial Temperature Range - Grade 6 device.
V
CC
Noise And Negative Going Transients
I
CC
transients, including those produced by output
switching, can produce voltage fluctuations, re-
sulting in spikes on the V
CC
bus. These transients
can be reduced if capacitors are used to store en-
ergy which stabilizes the V
CC
bus. The energy
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic by-
pass capacitor value of 0.1μF (as shown in Figure
8) is recommended in order to provide the needed
filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate neg-
ative voltage spikes on V
CC
that drive it to values
below V
SS
by as much as one volt. These negative
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, STMicroelectronics recom-
mends connecting a schottky diode from V
CC
to
V
SS
(cathode connected to V
CC
, anode to V
SS
).
Schottky diode 1N5817 is recommended for
through hole and MBRS120T3 is recommended
for surface mount.
Figure 8. Supply Voltage Protection
Symbol
Parameter
(1)
Min
Max
Unit
t
F(2)
V
PFD
(max) to V
PFD
(min) V
CC
Fall Time
300
μs
t
FB(3)
V
PFD
(min) to V
SS
V
CC
Fall Time
10
μs
t
R
V
PFD
(min) to V
PFD
(max) V
CC
Rise Time
10
μs
t
RB
V
SS
to V
PFD
(min) V
CC
Rise Time
1
μs
t
EDL
Chip Enable Propagation Delay
M40Z111
15
ns
M40Z111W
20
ns
t
EDH
Chip Enable Propagation Delay
M40Z111
10
ns
M40Z111W
20
ns
t
ER(4)
Chip Enable Recovery
40
200
ms
t
WPT
Write Protect Time
M40Z111
40
150
μs
M40Z111W
40
250
μs
AI00622
VCC
0.1
μ
F
DEVICE
VCC
VSS
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PDF描述 |
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| M40Z111WMH6 | 5V OR 3V NVRAM SUPERVISOR FOR UP TO TWO LPSRAMs |
| M40Z111WMH6TR | 5V OR 3V NVRAM SUPERVISOR FOR UP TO TWO LPSRAMs |
| M40Z111 | NVRAM Controller for up to Two LPSRAM(NVRAM控制器) |
| M40Z300AV | 3V NVRAM Supervisor for Up to 8 LPSRAMs |
| M40Z300AVMH1E | 3V NVRAM Supervisor for Up to 8 LPSRAMs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M40Z111SH | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:NVRAM CONTROLLER for up to TWO LPSRAM |
| M40Z111W | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V or 3V NVRAM supervisor for up to two LPSRAMs |
| M40Z111WMH | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:NVRAM CONTROLLER for up to TWO LPSRAM |
| M40Z111WMH6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V OR 3V NVRAM SUPERVISOR FOR UP TO TWO LPSRAMs |
| M40Z111WMH6E | 功能描述:監(jiān)控電路 N-Ch, 5V or 3V NVRAM up to 2 LPSRAMs RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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