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參數(shù)資料
| 型號： | M41ST85WMH6F |
| 廠商： | 意法半導體 |
| 英文描述： | 3.0/3.3V I2C Combination Serial RTC, NVRAM Supervisor and Microprocessor Supervisor |
| 中文描述： | 3.0/3.3V的I2C串行時鐘組合，NVRAM中監(jiān)督員和微處理器監(jiān)控 |
| 文件頁數(shù)： | 12/34頁 |
| 文件大小： | 226K |
| 代理商： | M41ST85WMH6F |
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M41ST85W
12/34
WRITE Mode
In this mode the master transmitter transmits to
the M41ST85W slave receiver. Bus protocol is
shown in
Figure 14.
. Following the START condi-
tion and slave address, a logic '0' (R/W=0) is
placed on the bus and indicates to the addressed
device that word address An will follow and is to be
written to the on-chip address pointer. The data
word to be written to the memory is strobed in next
and the internal address pointer is incremented to
the next memory location within the RAM on the
reception of an acknowledge clock. The
M41ST85W slave receiver will send an acknowl-
edge clock to the master transmitter after it has re-
ceived
the
slave
address
11., page 10
) and again after it has received the
word address and each data byte.
(see
Figure
Figure 14. WRITE Mode Sequence
Data Retention Mode
With valid V
CC
applied, the M41ST85W can be ac-
cessed as described above with READ or WRITE
Cycles. Should the supply voltage decay, the
M41ST85W will automatically deselect, write pro-
tecting itself (and any external SRAM) when V
CC
falls between V
PFD
(max) and V
PFD
(min). This is
accomplished by internally inhibiting access to the
clock registers. At this time, the Reset pin (RST) is
driven active and will remain active until V
CC
re-
turns to nominal levels. External RAM access is in-
hibited in a similar manner by forcing E
CON
to a
high level. This level is within 0.2 volts of the V
BAT
.
E
CON
will remain at this level as long as V
CC
re-
mains at an out-of-tolerance condition. When V
CC
falls below the Battery Back-up Switchover Volt-
age (V
SO
), power input is switched from the V
CC
pin to the SNAPHAT
battery, and the clock regis-
ters and external SRAM are maintained from the
attached battery supply.
All outputs become high impedance. The V
OUT
pin
is capable of supplying 100 μA of current to the at-
tached memory with less than 0.3 volts drop under
this condition. On power up, when V
CC
returns to
a nominal value, write protection continues for t
rec
by inhibiting E
CON
. The RST signal also remains
active during this time (see
Figure 22., page 27
).
Note:
Most low power SRAMs on the market to-
day can be used with the M41ST85W RTC SU-
PERVISOR. There are, however some criteria
which should be used in making the final choice of
an SRAM to use. The SRAM must be designed in
a way where the chip enable input disables all oth-
er inputs to the SRAM. This allows inputs to the
M41ST85W and SRAMs to be “Don’t Care” once
V
CC
falls below V
PFD
(min). The SRAM should also
guarantee data retention down to V
CC
=2.0 volts.
The chip enable access time must be sufficient to
meet the system needs with the chip enable output
propagation delays included. If the SRAM includes
a second chip enable pin (E2), this pin should be
tied to V
OUT
.
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0 volts. Manufacturers
generally specify a typical condition for room tem-
perature along with a worst case condition (gener-
ally at elevated temperatures). The system level
requirements will determine the choice of which
value to use. The data retention current value of
the SRAMs can then be added to the I
BAT
value of
the M41ST85W to determine the total current re-
quirements for data retention. The available bat-
tery capacity for the SNAPHAT
top of your choice
can then be divided by this current to determine
the amount of data retention available (see
Table
19., page 32
).
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
AI00591
BUS ACTIVITY:
A
S
A
A
A
A
S
S
P
SDA LINE
BUS ACTIVITY:
MASTER
R
DATA n
DATA n+1
DATA n+X
WORD
ADDRESS (An)
SLAVE
ADDRESS
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| M41ST85WMX6E | 3.0/3.3V I2C Combination Serial RTC, NVRAM Supervisor and Microprocessor Supervisor |
| M41ST85WMX6F | 3.0/3.3V I2C Combination Serial RTC, NVRAM Supervisor and Microprocessor Supervisor |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M41ST85WMH6F-CUT TAPE | 制造商:ST 功能描述:M41ST Series 3.3 V I2C Serial RTC NVRAM / Microprocessor Superviser - SOH-28 |
| M41ST85WMH6TR | 功能描述:實時時鐘 Advanced Analog RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| M41ST85WMSX6 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| M41ST85WMX | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 OR 3.0V, 512 bit 64 x 8 SERIAL RTC and NVRAM SUPERVISOR |
| M41ST85WMX6 | 功能描述:實時時鐘 Serial 512 (64x8) RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
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