參數(shù)資料
型號(hào): M41ST85WMH6F
廠商: 意法半導(dǎo)體
英文描述: 3.0/3.3V I2C Combination Serial RTC, NVRAM Supervisor and Microprocessor Supervisor
中文描述: 3.0/3.3V的I2C串行時(shí)鐘組合,NVRAM中監(jiān)督員和微處理器監(jiān)控
文件頁數(shù): 20/34頁
文件大?。?/td> 226K
代理商: M41ST85WMH6F
M41ST85W
20/34
Power-on Reset
The M41ST85W continuously monitors V
CC
.
When V
CC
falls to the power fail detect trip point,
the RST pulls low (open drain) and remains low on
power-up for t
rec
after V
CC
passes V
PFD
(max).
The RST pin is an open drain output and an appro-
priate pull-up resistor should be chosen to control
rise time.
Reset Inputs (RSTIN1 & RSTIN2)
The M41ST85W provides two independent inputs
which can generate an output reset. The duration
and function of these resets is identical to a reset
generated by a power cycle.
Table 5.
and
Figure
19.
illustrate the AC reset characteristics of this
function. Pulses shorter than t
RLRH1
and t
RLRH2
will not generate a reset condition. RSTIN1
and
RSTIN2 are each internally pulled up to V
CC
through a 100k
resistor.
Figure 19. RSTIN1 & RSTIN2 Timing Waveforms
Note: With pull-up resistor
Table 5. Reset AC Characteristics
Note: 1. Valid for Ambient Operating Temperature: T
A
= –40 to 85°C; V
CC
= 2.7 to 3.6V (except where noted).
2. Pulse width less than 50ns will result in no RESET (for noise immunity).
3. Pulse width less than 20ms will result in no RESET (for noise immunity).
4. Programmable (see
Table 6., page 22
).
Symbol
Parameter
(1)
Min
Max
Unit
t
RLRH1(2)
RSTIN1 Low to RSTIN1 High
200
ns
t
RLRH2(3)
RSTIN2 Low to RSTIN2 High
100
ms
t
R1HRH(4)
RSTIN1 High to RST High
40
200
ms
t
R2HRH(4)
RSTIN2 High to RST High
40
200
ms
AI03665
RSTIN2
RST
(1)
RSTIN1
tRLRH1
tRLRH2
tR1HRH
tR2HRH
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