參數(shù)資料
型號(hào): M41T00AUDD1E
廠商: STMICROELECTRONICS
元件分類: 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: REAL TIME CLOCK, DSO16
封裝: 5 X 4 MM, ROHS COMPLIANT, DFN-16
文件頁數(shù): 26/42頁
文件大小: 333K
代理商: M41T00AUDD1E
Initial conditions
M41T00AUD
8
Initial conditions
The first time the M41T00AUD is powered up, some of its registers will automatically have
their bits set to pre-determined levels as depicted in the Table 5. Typically, these values are
set to benign levels to ensure predictable operation of the device.
ST, the stop bit, is a 0 at first power-up thus enabling the oscillator to run without need of
user intervention. On subsequent power-ups, it is not altered by the device and remains at
the last value programmed by the user. All other bits listed as unchanged (UC) in the table
behave similarly during power cycles.
The HT or halt bit is always set to 1 thus halting updates of the transfer buffer registers. The
user must write it to 0 to allow updates to resume.
The discrete output function available on the IRQ/FT/OUT pin is set to 1. This is an open
drain output, and thus a 1 represents a high impedance condition.
FT or frequency test is always disabled on power-ups. The OF or oscillator fail bit will
always be 1 on the first power-up since the oscillator is always off prior to the first application
of VCC.
The trickle charger is always turned completely off after any power-up. The bits affecting it
are set to levels which keep all the trickle charge switches open. Both TCH2 and TCFE are
0 which opens their corresponding switches. TCHE3:TCHE0 are set to Ah, which is the
exact opposite of the value (5) required to close the corresponding switch.
On first power-up, the tone selects bits, 256/512 and TONE, are set to select the 512 hertz
tone, but have the function disabled (see Section 7). On subsequent power-ups, the
256/512 select bit remains unchanged, but TONE is always cleared. Furthermore, the
MUTE bit is always set to MUTE on all power-ups, disabling all audio.
The four-bit audio gain value is always set to the lowest setting (0) on initial power-up, but
remains unaffected by subsequent power cycles.
The 5-bit calibration register and its associated sign bit are set to 0 on initial power-up thus
resulting in no correction applied to the timekeeping operation. On subsequent power-ups,
the contents are not altered.
Table 8.
Initial values
Condition
ST
HT OUT FT OF OFIE
TCHE
3:0
TCH2 TCFE
256
512
TONE MUTE
GAIN
Cali-
bration
Initial
power-up(1)
1.
State of other control bits undefined
0
On
11
0
1
0
Off
Ah
Off
0
Off
0
Off
1
512
0
Off
1
MUTE
0
–33 dB
0
Subsequent
power-up
(with
battery
backup)
UC(2)
2.
UC = unchanged
1
UC
0
UC
Ah
Off
0
Off
0
Off
UC
0
Off
1
MUTE
UC
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