參數(shù)資料
型號: M41T00AUDD1E
廠商: STMICROELECTRONICS
元件分類: 時鐘/數(shù)據(jù)恢復及定時提取
英文描述: REAL TIME CLOCK, DSO16
封裝: 5 X 4 MM, ROHS COMPLIANT, DFN-16
文件頁數(shù): 7/42頁
文件大小: 333K
代理商: M41T00AUDD1E
M41T00AUD
Operation
4.4
WRITE mode
In this mode the master transmitter transmits to the M41T00AUD slave receiver. Bus
protocol is shown in Figure 11. Following the START condition and slave address, a logic '0'
(R/W = 0) is placed on the bus and indicates to the addressed device that word address An
will follow and is to be written to the on-chip address pointer. The data word to be written to
the device is strobed in next and the internal address pointer is incremented to the next
location within the device on the reception of an acknowledge clock. The M41T00AUD slave
receiver will send an acknowledge clock to the master transmitter after it has received the
slave address and again after it has received the word address and each data byte (see
Figure 11.
WRITE mode sequence
4.5
Data retention mode
With valid VCC applied, the M41T00AUD can be accessed as described above with READ
or WRITE cycles. Should the supply voltage decay, the M41T00AUD will automatically
deselect, write protecting itself when VCC falls (see Figure 13).
AI00591
BUS ACTIVITY:
AC
K
S
AC
K
AC
K
AC
K
AC
K
ST
OP
ST
AR
T
P
SDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n
DATA n+1
DATA n+X
WORD
ADDRESS (An)
SLAVE
ADDRESS
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