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參數(shù)資料
| 型號： | M41T11MH6F |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Serial Real Time Clock with 56 Bytes of NVRAM |
| 中文描述： | 串行實時時鐘與56字節(jié)的NVRAM |
| 文件頁數(shù)： | 13/29頁 |
| 文件大小： | 154K |
| 代理商： | M41T11MH6F |
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M41T11
Operation
13/29
2.3
WRITE Mode
In this mode the master transmitter transmits to the M41T11 slave receiver. Bus protocol is shown in
Figure 8
. Following the START condition and slave address, a logic '0' (R/W = 0) is placed on the bus and
indicates to the addressed device that word address An will follow and is to be written to the on-chip
address pointer. The data word to be written to the memory is strobed in next and the internal address
pointer is incremented to the next memory location within the RAM on the reception of an acknowledge
clock. The M41T11 slave receiver will send an acknowledge clock to the master transmitter after it has
received the slave address and again after it has received the word address and each data byte (see
Figure 7 on page 10
).
2.4
Data retention Mode
With valid V
CC
applied, the M41T11 can be accessed as described above with read or write cycles.
Should the supply voltage decay, the M41T11 will automatically deselect, write protecting itself when V
CC
falls (see
Figure 15
).
Figure 11.
WRITE Mode sequence
AI00591
BUS ACTIVITY:
A
S
A
A
A
A
S
S
P
SDA LINE
BUS ACTIVITY:
MASTER
R
DATA n
DATA n+1
DATA n+X
WORD
ADDRESS (An)
SLAVE
ADDRESS
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