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參數(shù)資料
| 型號： | M48Z02 |
| 廠商： | 意法半導體 |
| 英文描述： | 16 Kbit 2Kb x 8 ZEROPOWER SRAM |
| 中文描述： | 16千位2KB的SRAM的× 8 ZEROPOWER |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 85K |
| 代理商： | M48Z02 |
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
–40 to 85
°
C
T
STG
T
SLD (2)
Storage Temperature (V
CC
Off)
–40 to 85
°
C
Lead Solder Temperature for 10 seconds
260
°
C
V
IO
Input or Output Voltages
–0.3 to 7
V
V
CC
Supply Voltage
–0.3 to 7
V
I
O
Output Current
20
mA
P
D
Power Dissipation
1
W
Notes:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability.
2. Soldering temperature not to exceed 260
°
C for 10 seconds (total thermal budget not to exceed 150
°
C for longer than 30 seconds).
CAUTION:
Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
Table 2. Absolute Maximum Ratings
(1)
Mode
V
CC
E
G
W
DQ0-DQ7
Power
Deselect
4.75V to 5.5V
or
4.5V to 5.5V
V
IH
X
X
High Z
Standby
Write
V
IL
X
V
IL
D
IN
Active
Read
V
IL
V
IL
V
IH
D
OUT
Active
Read
V
IL
V
IH
V
IH
High Z
Active
Deselect
V
SO
to V
PFD
(min)
X
X
X
High Z
CMOS Standby
Deselect
≤
V
SO
X
X
X
High Z
Battery Back-up Mode
Notes
: X = V
IH
or V
IL
; V
SO
= Battery Back-up Switchover Voltage.
Table 3. Operating Modes
A1
A0
DQ0
DQ1
DQ2
VSS
A7
A6
A5
A4
A3
A2
A10
E
A8
A9
W
G
DQ7
DQ6
DQ5
DQ4
DQ3
VCC
AI01187
M48Z02
M48Z12
8
9
10
11
12
1
2
3
4
5
6
7
16
15
14
13
24
23
22
21
20
19
18
17
Figure 2. DIP Pin Connections
The M48Z02/12 is a non-volatile pin and function
equivalent to any JEDEC standard 2K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes that
can be performed.
The M48Z02/12 also has its own Power-fail Detect
circuit. The control circuitry constantly monitors the
single 5V supply for an out of tolerance condition.
When V
CC
is out of tolerance, the circuit write
protects the SRAM, providing a high degree of data
security in the midst of unpredictable system op-
eration brought on by low V
CC
. As V
CC
falls below
approximately 3V, the control circuitry connects the
battery which maintains data and clock operation
until valid power returns.
DESCRIPTION
(cont’d)
2/12
M48Z02, M48Z12
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