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參數(shù)資料
| 型號： | M48Z02 |
| 廠商： | 意法半導體 |
| 英文描述： | 16 Kbit 2Kb x 8 ZEROPOWER SRAM |
| 中文描述： | 16千位2KB的SRAM的× 8 ZEROPOWER |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 85K |
| 代理商： | M48Z02 |
Symbol
Parameter
Min
Max
Unit
t
PD
E or W at V
IH
before Power Down
0
μ
s
t
F (1)
V
PFD
(max) to V
PFD
(min) V
CC
Fall Time
300
μ
s
t
FB (2)
V
PFD
(min) to V
SO
V
CC
Fall Time
10
μ
s
t
R
V
PFD
(min) to V
PFD
(max) V
CC
Rise Time
0
μ
s
t
RB
V
SO
to V
PFD
(min) V
CC
Rise Time
1
μ
s
t
REC
E or W at V
IH
after Power Up
2
ms
Notes
: 1. V
PFD
(max) to V
PFD
(min) fall time of less than t
F
may result in deselection/write protection not occurring until 50
μ
s after
V
CC
passes V
PFD
(min).
2. V
PFD
(min) to V
SO
fall time of less than t
FB
may cause corruption of RAM data.
Table 8. Power Down/Up Mode AC Characteristics
(T
A
= 0 to 70
°
C or –40 to 85
°
C)
AI00606
VCC
VPFD (max)
INPUTS
(PER CONTROL INPUT)
OUTPUTS
DON'T CARE
HIGH-Z
tF
tFB
tR
tREC
tPD
tRB
tDR
VALID
VALID
NOTE
(PER CONTROL INPUT)
RECOGNIZED
RECOGNIZED
VPFD (min)
VSO
Figure 5. Power Down/Up Mode AC Waveforms
Note:
Inputs may or may not be recognized at this time. Caution should be taken to keep E
high as V
rises past V
(min). Some systems
may perform inadvertent write cycles after V
rises above V
(min) but before normal system operations begin. Even though a power on
reset is being applied to the processor, a reset condition may not occur until after the system clock is running.
5/12
M48Z02, M48Z12
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M48Z02_07 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V, 16Kbit (2Kb x 8) ZEROPOWER SRAM |
| M48Z02_10 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5 V, 16 Kbit (2 Kb x 8) ZEROPOWER? SRAM |
| M48Z02_11 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5 V, 16 Kbit (2 Kb x 8) ZEROPOWER?? SRAM |
| M48Z02-120PC1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:CMOS 8K x 8 TIMEKEEPER SRAM |
| M48Z02-120PC6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:CMOS 8K x 8 TIMEKEEPER SRAM |
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