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參數(shù)資料
| 型號： | M48Z19-100PC1 |
| 廠商： | 意法半導體 |
| 英文描述： | CMOS 8K x 8 ZEROPOWER SRAM |
| 中文描述： | 的CMOS 8K的× 8 ZEROPOWER的SRAM |
| 文件頁數(shù)： | 1/13頁 |
| 文件大小： | 122K |
| 代理商： | M48Z19-100PC1 |
AI01184
13
A0-A12
W
DQ0-DQ7
VCC
M48Z09
M48Z19
G
E2
VSS
8
E1
INT
Figure 1. Logic Diagram
M48Z09
M48Z19
CMOS 8K x 8 ZEROPOWER SRAM
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
UNLIMITED WRITE CYCLES
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
AUTOMATIC POWER-FAIL CHIP DESELECT and
WRITE PROTECTION
POWER-FAIL INTERRUPT
CHOICE of TWO WRITE PROTECT
VOLTAGES:
– M48Z09: 4.5V
≤
V
PFD
≤
4.75V
– M48Z19: 4.2V
≤
V
PFD
≤
4.5V
SELF CONTAINED BATTERY in the CAPHAT
DIP PACKAGE
11 YEARS of DATA RETENTION in the
ABSENCE of POWER
PIN and FUNCTION COMPATIBLE with the
MK48Z09, 19 and JEDEC STANDARD 8K x 8
SRAMs
DESCRIPTION
The M48Z09,19 ZEROPOWER
RAM is an 8K x 8
non-volatile static RAM which is pin and function
compatible with the MK48Z09,19.
A special 28 pin 600mil DIP CAPHAT
package
houses the M48Z09,19 silicon with a long life lith-
ium button cell to form a highly integrated battery
backed-up memory solution.
A0-A12
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
INT
Power Fail Interrupt
E1
Chip Enable 1
E2
Chip Enable 2
G
Output Enable
W
Write Enable
V
CC
Supply Voltage
V
SS
Ground
Table 1. Signal Names
28
1
PCDIP28 (PC)
Battery CAPHAT
November 1994
1/13
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PDF描述 |
|---|---|
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M48Z19PC | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:CMOS 8K x 8 ZEROPOWER SRAM |
| M48Z256-85PL1 | 制造商:STMicroelectronics 功能描述:512KX8 ZP 5% 85NS - Bulk |
| M48Z256Y-120PL1 | 制造商:STMicroelectronics 功能描述:256KX8 ZP 10% 120N - Bulk |
| M48Z256Y-85PL1 | 制造商:STMicroelectronics 功能描述:256KX8 ZP 10% 85NS - Bulk |
| M48Z2M1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:16 Mb 2Mb x 8 ZEROPOWER SRAM |
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