參數(shù)資料
型號(hào): M50LPW041N1T
廠商: 意法半導(dǎo)體
英文描述: 4 Mbit 512Kb x8, Uniform Block 3V Supply Low Pin Count Flash Memory
中文描述: 4兆位512KB的× 8,統(tǒng)一座3V電源低引腳數(shù)快閃記憶體
文件頁數(shù): 1/37頁
文件大?。?/td> 268K
代理商: M50LPW041N1T
1/37
PRELIMINARY DATA
September 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M50LPW041
4 Mbit (512Kb x8, Uniform Block)
3V Supply Low Pin Count Flash Memory
I
SUPPLY VOLTAGE
– V
CC
= 3V to 3.6V for Program, Erase and
Read Operations
– V
PP
= 12V for Fast Program and Fast Erase
I
LOW PIN COUNT (LPC)
– Standard Interface for embedded operation
with PC Chipsets that are without automap-
ping memory features
I
ADDRESS/ADDRESS MULTIPLEXED
– A/A Mux Interface for programming equip-
ment compatibility
I
LOW PIN COUNT (LPC) HARDWARE
INTERFACE MODE
– 5 Signal Communication Interface supporting
Read and Write Operations
– Hardware Write Protect Pins for Block Pro-
tection
– Register Based Read and Write Protection
– 5 Additional General Purpose Inputs for plat-
form design flexibility
– Synchronized with 33MHz PCI clock
I
BYTE PROGRAMMING TIME
– Single Byte Mode: 10μs (typical)
– Quadruple Byte Mode: 2.5μs (typical)
I
8 UNIFORM 64 Kbyte MEMORY BLOCKS
I
PROGRAM/ERASE CONTROLLER
– Embedded Byte Program and Block/Chip
Erase algorithms
– Status Register Bits
I
PROGRAM and ERASE SUSPEND
– Read other Blocks during Program/Erase
Suspend
– Program other Blocks during Erase Suspend
I
FOR USE in PC BIOS APPLICATIONS
I
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 3Ch
Figure 1. Logic Diagram (LPC Interface)
AI05785
4
LFRAME
LAD0-
LAD3
VCC
M50LPW041
CLK
VSS
4
IC
RP
TBL
5
INIT
WP
ID0-ID3
GPI0-
GPI4
VPP
PLCC32 (K)
TSOP40 (N)
10 x 20mm
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