參數(shù)資料
型號(hào)： M52D128168A-10BG
廠商： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類： DRAM
英文描述： 2M x 16 Bit x 4 Banks Synchronous DRAM
中文描述： 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54
封裝： 8 X 8 MM, LEAD FREE, FBGA-54
文件頁(yè)數(shù)： 6/47頁(yè)
文件大?。?/td> 1209K
代理商： M52D128168A-10BG
ES MT
M52D128168A
AC OPERATING TEST CONDITIONS
(V
DD
=1.8V
±
0.1V,T
A
= 0° ~ 70° )
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Preliminary
Elite Semiconductor Memory Technology Inc.
Revision
:
1.0
Publication Date
:
May. 2007
6/47
Value
Unit
V
V
ns
V
0.9 x V
DDQ
/ 0.2
0.5 x V
DDQ
tr / tf = 1 / 1
0.5 x V
DDQ
See Fig.2
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
-7.5
-10
Unit
Note
Row active to row active delay
t
RRD
(min)
15
20
ns
1
RAS to CAS delay
t
RCD
(min)
15
20
ns
1
Row precharge time
t
RP
(min)
15
20
ns
1
t
RAS
(min)
48
50
ns
1
Row active time
t
RAS
(max)
100
us
-
@Operating
t
RC
(min)
63
90
ns
1
Row cycle time
@Auto refresh
t
RFC
(min)
80
ns
1 , 5
Last data in to new col. Address delay
t
CDL
(min)
1
CLK
2
Last data in to row precharge
t
RDL
(min)
2
CLK
2
Last data in to burst stop
t
BDL
(min)
1
CLK
2
Col. Address to col. Address delay
t
CCD
(min)
1
CLK
3
Mode Register command to Active or Refresh Command
t
MRD
(min)
2
CLK
-
CAS latency=3
2
Number of valid output data
CAS latency=2
1
ea
4
Refresh period(4,096 rows)
t
BEF
(max)
64
ms
6
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks
5. A new command may be given t
RFC
after self refresh exit.
6. A maximum of eight consecutive AUTO REFRESH commands (with t
RFCmin
) can be posted to any given SDRAM,and
the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x15.
6μs.)
Z0=50
1.8V
Output
(Fig.2) ACOutput Load Circuit
20 pF
Vtt =0.5x VDDQ
VOH(DC) = VDDQ-0.2V, IOH = -0.1mA
VOL(DC) = 0.2V, IOL = 0.1mA
20 pF
Output
(Fig.1) DC Output Load circuit
10.6K
13.9K
50
相關(guān)PDF資料
PDF描述
M52D128168A-10TG 2M x 16 Bit x 4 Banks Synchronous DRAM
M52D128168A-7.5BG 2M x 16 Bit x 4 Banks Synchronous DRAM
M52D128168A-7.5TG 2M x 16 Bit x 4 Banks Synchronous DRAM
M52D16161A 512K x 16Bit x 2Banks Synchronous DRAM
M52D16161A-10BG 512K x 16Bit x 2Banks Synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M52D128168A-10BIG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Synchronous DRAM
M52D128168A-10TG 制造商:ELITE SEMICONDUCTOR 功能描述:SDRAM 128MB 1.8V 100MHZ TSOPII54
M52D128168A-10TIG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Synchronous DRAM
M52D128168A-7.5BG 制造商:ELITE SEMICONDUCTOR 功能描述:SDRAM 128MB 1.8V 133MHZ FBGA54 制造商:ELITE SEMICONDUCTOR 功能描述:SDRAM, 128MB, 1.8V, 133MHZ, FBGA54 制造商:ELITE SEMICONDUCTOR 功能描述:IC, SDRAM, 128MBIT, 133MHZ, FBGA-54; Memory Type:DRAM - Sychronous; Memory Configuration:2M x 16; Page Size:128MB; Memory Case Style:FBGA; No. of Pins:54; IC Interface Type:Parallel; Operating Temperature Min:0C; Frequency:133MHz ;RoHS Compliant: Yes
M52D128168A-7.5BIG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Synchronous DRAM
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