參數(shù)資料
型號(hào): M52D128168A-7.5TG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 2M x 16 Bit x 4 Banks Synchronous DRAM
中文描述: 8M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54
封裝: 0.400 INCH, LEAD FREE, TSOP2-54
文件頁數(shù): 4/47頁
文件大小: 1209K
代理商: M52D128168A-7.5TG
ES MT
M52D128168A
Preliminary
Elite Semiconductor Memory Technology Inc.
Revision
:
1.0
Publication Date
:
May. 2007
4/47
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
VALUE
UNIT
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-1.0 ~ 2.6
V
Voltage on V
DD
supply relative to V
SS
V
DD
, V
DDQ
-1.0 ~ 2.6
V
Storage temperature
T
STG
-55 ~ +150
C
°
Power dissipation
P
D
1
W
Short circuit current
I
OS
50
mA
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITION
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= 0 to 70 C
°
)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
NOTE
Supply voltage
V
DD
, V
DDQ
1.7
1.8
1.9
V
Input logic high voltage
V
IH
0.8xV
DDQ
1.8
V
DDQ
+0.3
V
1
Input logic low voltage
V
IL
-0.3
0
0.3
V
2
Output logic high voltage
V
OH
V
DDQ
-0.2
-
-
V
I
OH
= -0.1mA
Output logic low voltage
V
OL
-
-
0.2
V
μ
A
I
OL
= 0.1mA
Input leakage current
I
IL
-2
-
2
3
Output leakage current
I
OL
-2
-
2
μ
A
4
Note:
1. V
IH(max)
= 2.2V AC for pulse width
3ns acceptable.
2. V
IL(min)
= -1.0V AC for pulse width
3ns acceptable.
3. Any input 0V
V
IN
V
DDQ
, all other pins are not under test = 0V.
4. D
out
is disabled , 0V
V
OUT
V
DDQ
.
CAPACITANCE
(V
DD
= 1.8V, T
A
= 25 C
°
, f = 1MHZ)
PARAMETER
SYMBOL
MIN
MAX
UNIT
Input capacitance (A0 ~ A11, BA0 ~ BA1)
C
IN1
1.5
3.0
pF
Input capacitance
(CLK, CKE, CS , RAS , CAS ,
WE
&
L(U)DQM)
C
IN2
1.5
3.5
pF
Data input/output capacitance (DQ0 ~ DQ15)
C
OUT
2.0
4.5
pF
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