參數(shù)資料
型號(hào): M52D32321A
廠商: Elite Semiconductor Memory Technology Inc.
英文描述: 512K x 32Bit x 2Banks Synchronous DRAM
中文描述: 為512k × 32Bit的x 2Banks同步DRAM
文件頁數(shù): 21/29頁
文件大小: 707K
代理商: M52D32321A
ES MT
Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4
M52D32321A
Elite Semiconductor Memory Technology Inc.
Publication Date
:
May. 2007
Revision
:
1.3
21/29
*Note:1.DQM is needed to prevent bus contention.
C L O C K
C K E
A D D R
DQ
DQ M
A10/AP
Ra
Ca
Cb
C c
Ra
Qa0
Qa1
Qa2
Qa3
t
S H Z
Qb1
Qb0
t
S H Z
Dc0
Dc2
*Not e 1
Row Active
Read
Clock
Suspension
Read
Read DQM
W rite
W rite
DQ M
Clock
Suspension
W rite
DQ M
:Don't Care
BA
CS
RAS
CAS
W E
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
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