ES MT

Self Refresh Entry & Exit Cycle

M52D32321A

Elite Semiconductor Memory Technology Inc.

Publication Date

:

May. 2007

Revision

:

1.3

26/29

*Note: TO ENTER SELF REFRESH MODE

1. CS ,RAS & CAS with CKE should be low at the same clock cycle.

2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.

3. The device remains in self refresh mode as long as CKE stays “Low”.

cf.) Once the device enters self refresh mode, minimum t

RAS

is required before exit from self refresh.

TO EXIT SELF REFRESH MODE

4. System clock restart and be stable before returning CKE high.

5. CS Starts from high.

6. Minimum t

RC

is required after CKE going high to complete self refresh exit.

7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst

refresh.

C L O C K

C K E

A D D R

DQ

DQ M

A10/AP

S el f R ef r es h E n t r y

A u t o R ef r es h

: D o n ' t c a r e

S e l f R ef r e s h E xi t

H i - Z

H i - Z

W E

BA

CAS

RAS

CS

*Not e 2

*Not e 1

*Not e 4

t

RCm i n

* Not e 6

*Not e 5

*Not e 7

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

t

S S

*Note3