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參數(shù)資料
| 型號： | M52S128168A-10TG |
| 廠商： | ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 1M x 16 Bit x 4 Banks Synchronous DRAM |
| 中文描述： | 8M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| 封裝： | 0.400 INCH, LEAD FREE, TSOP2-54 |
| 文件頁數(shù)： | 28/47頁 |
| 文件大?。?/td> | 1213K |
| 代理商： | M52S128168A-10TG |
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ES MT
Current
State
Precharging
Row
Activating
Refreshing
Mode
Register
Accessing
Abbreviations :
Preliminary
M52S128168A
Elite Semiconductor Memory Technology Inc.
Revision
:
1.0
Publication Date
:
May. 2007
28/47
CS
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
RAS CAS
X
H
H
H
L
L
L
X
H
H
H
L
L
L
X
H
H
L
L
X
H
H
H
L
WE
X
H
L
X
H
L
X
X
H
L
X
H
L
X
X
X
X
X
X
X
H
L
X
X
BA
ADDR
ACTION
Note
X
H
H
L
H
H
L
X
H
H
L
H
H
L
X
H
L
H
L
X
H
H
L
X
X
X
X
BA
BA
BA
X
X
X
X
BA
BA
BA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CA
RA
NOP
Idle after tRP
NOP
Idle after tRP
ILLEGAL
ILLEGAL
ILLEGAL
NOP
Idle after tRP
ILLEGAL
NOP
Row Active after tRCD
NOP
Row Active after tRCD
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP
Idle after tRFC
NOP
Idle after tRFC
ILLEGAL
ILLEGAL
ILLEGAL
NOP
Idle after 2clocks
NOP
Idle after 2clocks
ILLEGAL
ILLEGAL
ILLEGAL
2
2
2
4
2
2
2
2
A10/AP
X
X
X
X
CA
RA
A10/AP
X
X
X
X
X
X
X
X
X
X
X
RA = Row Address
NOP = No Operation Command
BA = Bank Address
CA = Column Address
AP = Auto Precharge
*Note : 1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle.
2. Illegal to bank in specified state ; Function may be legal in the bank indicated by BA, depending on the state of the
bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharge or in idle state. May precharge bank indicated by BA (and A10/AP).
5. Illegal if any bank is not idle.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M52S128168A-7.5BG | 1M x 16 Bit x 4 Banks Synchronous DRAM |
| M52S128168A-7.5TG | 1M x 16 Bit x 4 Banks Synchronous DRAM |
| M52S16161A | 512K x 16Bit x 2Banks Synchronous DRAM |
| M52S16161A-10BG | 512K x 16Bit x 2Banks Synchronous DRAM |
| M52S16161A-10TG | 512K x 16Bit x 2Banks Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M52S128168A-7.5BG | 制造商:ELITE SEMICONDUCTOR 功能描述:SDRAM 128MB 2.5V 133MHZ FBGA54 制造商:ELITE SEMICONDUCTOR 功能描述:SDRAM, 128MB, 2.5V, 133MHZ, FBGA54 制造商:ELITE SEMICONDUCTOR 功能描述:DRAM IC; Page Size:128MB; Memory Case Style:FBGA; No. of Pins:54; IC Interface Type:Parallel; Operating Temperature Min:0C; Operating Temperature Max:70C; Filter Terminals:Surface Mount; Frequency:133MHz; Interface Type:Parallel ;RoHS Compliant: Yes |
| M52S128168A-7.5TG | 制造商:ELITE SEMICONDUCTOR 功能描述:SDRAM 128MB 2.5V 133MHZ TSOPII54 |
| M52S128168A-7BG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Synchronous DRAM |
| M52S128168A-7TG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Synchronous DRAM |
| M52S128324A | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM |
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