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  • 參數(shù)資料
    型號(hào): M58BW016BB90ZA6
    廠商: STMICROELECTRONICS
    元件分類: PROM
    英文描述: 512K X 32 FLASH 3V PROM, 90 ns, PBGA80
    封裝: 10 X 12 MM, 1 MM PITCH, LBGA-80
    文件頁(yè)數(shù): 35/63頁(yè)
    文件大?。?/td> 895K
    代理商: M58BW016BB90ZA6
    40/63
    Table 20. Synchronous Burst Read AC Characteristics
    Note: 1. Data output should be read on the valid clock edge.
    2. For other timings see Table 16, Asynchronous Bus Read Characteristics.
    Figure 15. Synchronous Burst Read (Data Valid from ’n’ Clock Rising Edge)
    Note: For set up signals and timings see Synchronous Burst Read.
    Symbol
    Parameter
    Test Condition
    M58BW016
    Unit
    80
    90
    100
    tAVLL
    Address Valid to Latch Enable Low
    E = VIL
    Min
    0
    ns
    tBHKH
    Burst Address Advance High to Valid Clock
    Edge
    E = VIL, G = VIL,
    L = VIH
    Min
    8
    ns
    tBLKH
    Burst Address Advance Low to Valid Clock
    Edge
    E = VIL, G = VIL,
    L = VIH
    Min
    8
    ns
    tELLL
    Chip Enable Low to Latch Enable low
    Min
    0
    ns
    tGLQV
    Output Enable Low to Output Valid
    E = VIL, L = VIH
    Min
    25
    ns
    tKHAX
    Valid Clock Edge to Address Transition
    E = VIL
    Min
    5
    ns
    tKHLL
    Valid Clock Edge to Latch Enable Low
    E = VIL
    Min
    0
    ns
    tKHLX
    Valid Clock Edge to Latch Enable Transition
    E = VIL
    Min
    0
    ns
    tKHQX
    Valid Clock Edge to Output Transition
    E = VIL, G = VIL,
    L = VIH
    Min
    3
    ns
    tLLKH
    Latch Enable Low to Valid Clock Edge
    E = VIL
    Min
    6
    ns
    tQVKH
    (1)
    Output Valid to Valid Clock Edge
    E = VIL, G = VIL,
    L = VIH
    Min
    6
    ns
    tRLKH
    Valid Data Ready Low to Valid Clock Edge
    E = VIL, G = VIL,
    L = VIH
    Min
    6
    ns
    tKHQV
    Valid Clock Edge to Output Valid
    E = VIL, G = VIL,
    L = VIH
    Max
    11
    ns
    AI04408b
    K
    n+5
    n+4
    n+3
    n+2
    n+1
    n
    DQ0-DQ31
    tQVKH
    tKHQX
    Q0
    Q1
    Q2
    Q3
    Q4
    Q5
    SETUP
    Burst Read
    Q0 to Q3
    tKHQV
    Note: n depends on Burst X-Latency
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