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參數(shù)資料
| 型號(hào)： | M59DR032B120ZB1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 32 Mbit 2Mb x16, Dual Bank, Page Low Voltage Flash Memory |
| 中文描述： | 32兆位的2Mb x16插槽，雙行，第低壓閃存 |
| 文件頁(yè)數(shù)： | 7/38頁(yè) |
| 文件大?。?/td> | 270K |
| 代理商： | M59DR032B120ZB1T |
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M59DR032A, M59DR032B
Table 8. User Bus Operations
(1)
Note: 1. X = Don’t care.
Table 9. Read Electronic Signature (AS and Read CFI instructions)
Table 10. Read Block Protection (AS and Read CFI instructions)
Table 11. Read Configuration Register (AS and Read CFI instructions)
Operation
E
G
W
RP
WP
DQ15-DQ0
Write
V
IL
V
IH
V
IL
V
IH
V
IH
Data Input
Output Disable
V
IL
V
IH
V
IH
V
IH
V
IH
Hi-Z
Standby
V
IH
X
X
V
IH
V
IH
Hi-Z
Reset / Power Down
X
X
X
V
IL
V
IH
Hi-Z
Block Locking
V
IL
X
X
V
IH
V
IL
X
Code
Device
E
G
W
A0
A1
A7-A2
Other
Addresses
DQ15-DQ8
DQ7-DQ0
Manufacturer Code
V
IL
V
IL
V
IH
V
IL
V
IL
0
Don’t Care
00h
20h
Device Code
M59DR032A
V
IL
V
IL
V
IH
V
IH
V
IL
0
Don’t Care
00h
A0h
M59DR032B
V
IL
V
IL
V
IH
V
IH
V
IL
0
Don’t Care
00h
A1h
Block Status
E
G
W
A0
A1
A20-A12
A7-A2
Other
Addresses
DQ0
DQ1
DQ15-DQ2
Protected Block
V
IL
V
IL
V
IH
V
IL
V
IH
Block Address
0
Don’t Care
1
0
0000h
Unprotected Block
V
IL
V
IL
V
IH
V
IL
V
IH
Block Address
0
Don’t Care
0
0
0000h
Locked Block
V
IL
V
IL
V
IH
V
IL
V
IH
Block Address
0
Don’t Care
X
1
0000h
RP Function
E
G
W
A0
A1
A7-A2
Other Addresses
DQ10
DQ9-DQ0
DQ15-DQ11
Reset
V
IL
V
IL
V
IH
V
IH
V
IH
0
Don’t Care
0
Don’t Care
Reset/Power Down
V
IL
V
IL
V
IH
V
IH
V
IH
0
Don’t Care
1
Don’t Care
Automatic Standby.
When in Read mode, after
150ns of bus inactivity and when CMOS levels are
driving the addresses, the chip automatically en-
ters a pseudo-standby mode where consumption
is reduced to the CMOS standby value, while out-
puts still drive the bus.
Power Down.
The memory is in Power Down
when the Configuration Register is set for Power
Down and RP is at V
IL
. The power consumption is
reduced to the Power Down level, and Outputs are
in high impedance, independent of the Chip En-
able E, Output Enable G or Write Enable W inputs.
Block Locking.
Any combination of blocks can
be temporarily protected against Program or
Erase by setting the lock register and pulling WP
to V
IL
(see Block Lock instruction).
Dual Bank Operations.
The Dual Bank allows to
read data from one bank of memory while a pro-
gram or erase operation is in progress in the other
bank of the memory. Read and Write cycles can
be initiated for simultaneous operations in different
banks without any delay. Status Register during
Program or Erase must be monitored using an ad-
dress within the bank being modified.
Output Disable.
The data outputs are high im-
pedance when the Output Enable G is at V
IH
with
Write Enable W at V
IH
.
Standby.
The memory is in standby when Chip
Enable E is at V
IH
and the P/E.C. is idle. The pow-
er consumption is reduced to the standby level
and the outputs are high impedance, independent
of the Output Enable G or Write Enable W inputs.
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