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參數(shù)資料
| 型號： | M5M4V16169DRT-15 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| 中文描述： | 16MCDRAM：16米（100萬字由16位）與16K的緩存內存（1024字由16位）的SRAM |
| 文件頁數(shù)： | 15/64頁 |
| 文件大?。?/td> | 737K |
| 代理商： | M5M4V16169DRT-15 |
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M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MITSUBISHI LSIs
(REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
DRAM Write
Transfer3
Data (8X16 Block) is transferred from WB1 through WB2 to the DRAM block specified by
Addresses Ad3-Ad7. Addresses Ad8-Ad9 must be set to Low. The Mask present in Byte
MaskRegister controls the data written to the DRAM. The Byte Mask Register is set at Load Byte
Mask cycle,where corresponding byte masks are set depending on DQ data in the cycle. (Note
4,5) The data of WB1 and the mask data of WBM1 are tranferred to WB2 and WBM2, however
WBM1/2 is not used in this cycle.
DRAM
256KX16
Ad3-7
1of32
Decode
DRAM RowDecoder
DRAM Write
Transfer3
& Read
Data (8X16 Block) is transferred from WB1 through WB2 to the DRAM block specified by
Addresses Ad3-Ad7. Addresses Ad8-Ad9 must be set to Low. The Mask present in Byte
MaskRegister controls the data written to the DRAM. The block to which the data is written in
DRAM is simultaneously transferred to the Read Buffer.(Notes 1,2,4,5)
DRAM
256KX16
Ad3-7
1of32
Decode
DRAM RowDecoder
MODE DESCRIPTIONS (8)
15
X
DQs
SRAM
1KX16
8X16
8X16
8X16
8X16
8X16
16bits
16bits
16bits
As3-9
1of128Decode
SRAM RowDecoder
Ad0-11
1of4096Decode
As0-2
1of8
Decode
As0-2
1of8Decode
8X16Block
8X16Block
WB1
Upper Byte
Lower Byte
Upper Byte
Lower Byte
16bits
As0-2
1of8Decode
Lower Byte
RB2
Lower Byte
RB1
X
DQs
SRAM
1KX16
8X16
8X16
8X16
8X16
8X16
16bits
16bits
16bits
As3-9
1of128Decode
SRAM RowDecoder
Ad0-11
1of4096Decode
As0-2
1of8
Decode
As0-2
1of8Decode
8X16Block
8X16Block
WB1
Upper Byte
Lower Byte
Upper Byte
Lower Byte
16bits
As0-2
1of8Decode
Lower Byte
RB2
Lower Byte
RB1
DQ8-15
DQ0-7
DQ8-15
DQ0-7
相關PDF資料 |
PDF描述 |
|---|---|
| M5M4V16169DRT-7 | 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DRT-8 | 22182053 |
| M5M4V16G50DFP-10 | 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM |
| M5M4V16G50DFP-12 | 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM |
| M5M4V16G50DFP-8 | 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M5M4V16169DRT-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DRT-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DTP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DTP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DTP-15 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
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