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參數(shù)資料
| 型號： | M5M4V16169DRT-7 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| 中文描述： | 16MCDRAM：16米（100萬字由16位）與16K的緩存內(nèi)存（1024字由16位）的SRAM |
| 文件頁數(shù)： | 12/64頁 |
| 文件大?。?/td> | 737K |
| 代理商： | M5M4V16169DRT-7 |
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M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MODE DESCRIPTIONS (5)
MITSUBISHI LSIs
(REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
12
DRAM Read
Transfer
A Block (8x16) is transferred from the DRAM to the Read Buffer1 and 2 (RB1,RB2) as specified
by Addresses Ad3-Ad7. Addresses Ad8-Ad11 and Ad0-Ad2 must be set to Low. After the
Latency Period (specified in the Access Latency Table) new data will be present in the Read
Buffer2. Prior to the Latency timeout, old data will be present in the RB2. (Notes 1,2,4)
DRAM
Power-Down
DRAM NOP
If CMd#=Low at the rising edge of K, the DRAM enters DRAM Power Down at the next rising
edge of K. During this mode, the internal DRAM K clock becomes inactive. Also all input
buffers of DRAM clocks and DRAM addresses are inactive. Note that the latency of DRAM
Read Transfer cycle is not counted up in this cycle.
The DNOP cycle is used when no other DRAM operations are desired, holding the DRAM in
its present (precharge/activate) state.
DQs
SRAM
1KX16
8X16
8X16
8X16
8X16
8X16
16bits
16bits
16bits
As3-9
1of128Decode
SRAM RowDecoder
DRAM
1M X 16
Ad0-11
1of4096Decode
Ad3-7
1of32
Decode
As0-2
1of8
Decode
As0-2
1of8Decode
8X16Block
8X16Block
WB1
Upper Byte
Lower Byte
DRAM RowDecoder
16bits
As0-2
1of8Decode
Upper Byte
Lower Byte
RB2
Upper Byte
Lower Byte
RB1
X
Upper Byte
Lower Byte
DQ8-15
DQ0-7
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| M5M4V16169DRT-8 | 22182053 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M5M4V16169DRT-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DTP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DTP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DTP-15 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DTP-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
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