參數(shù)資料
型號(hào)： M5M4V16169DRT-7
廠商： Mitsubishi Electric Corporation
英文描述： 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
中文描述： 16MCDRAM：16米（100萬字由16位）與16K的緩存內(nèi)存（1024字由16位）的SRAM
文件頁數(shù)： 6/64頁
文件大?。?/td> 737K
代理商： M5M4V16169DRT-7
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MITSUBISHI LSIs
(REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
6
Master Clock Provides the fundamental timing and the internal clock frequency for
the CDRAM. All external timing parameters (with the exception of G# in read cycle
and CMd# in Self refresh cycle) are specified with respect to the rising edge of K.
DRAM Clock Mask controls the operation of the internal DRAM master clock (K).
When CMd# is Low at the rising edge of K, the internal DRAM master clock (K) for
the following cycle is ceased and input stages are powered-off, resulting in a DRAM
Power Down.
Row Address Strobe is used in conjunction with Master clock K (depending on the
states of CMd#, CAS#, and DTD#) to activate the DRAM (latching the Row Address
lines and accessing 1 of 4096 rows), initiate a DRAM precharge cycle, perform a
DRAM Read or Write Transfer, DRAM Write Transfer & Read, set the command
registers, start an Auto-Refresh cycle, enter a Self-Refresh cycle,create a DRAM
NOP cycle, or power down the DRAM.
Column Address Strobe is used in conjunction with the Master Clock K to latch the
Column addresses. When preceded by RAS# in a DRAM access cycle, CAS#
initiates a DRAM Write Transfer (WB1/2 -> DRAM, if DTD#=L), DRAM Write
Transfer & Read (WB1/2 -> DRAM -> RB, if DTD#=L) or DRAM Read Transfer
(DRAM -> RB, if DTD#=H), depending on the state of DTD# (see DTD# pin
description).
Data Transfer Direction controls DRAM-to-RB(read) / WB-to-DRAM (write)
direction. If preceded by a RAS# low cycle, both CAS# and DTD# low (on the
rising edge of K) initiate a DRAM Write Transfer cycle. If DTD# stays High with the
above conditions, a DRAM Read Transfer cycle results. DTD# can also initiate
DRAM Activate, DRAM Precharge, Auto-Refresh, Set-Command Register, and
Self Refresh cycles.
DRAM Address Lines are Multiplexed to reduce pin count.
RAS=low,CAS=high,DTD=high, K=Rising edge) specify the Row Address of the
DRAM to activate and refresh the selected page and Ad3-Ad7 (@
RAS=high,CAS=low,K=Rising edge) specify the Block Address of the DRAM. In
addition, Ad0-Ad2 (@ RAS=high,CAS=low, K=Rising edge) specify the transfer
operation of the DRAM . Also Ad0-Ad9 (@RAS=low,CAS=low, DTD=low,
K=Rising Edge) are used as the command in set command register cycle.
Ad0-Ad11 (@
The Chip Select controls the operation of the CDRAM. When CS#=H at the rising
edge of K and the previous CMd# or CMs# is high, the chip is in No Operation
mode.
SRAM Clock Mask controls the operation of the internal SRAM master clock (Ks).
When CMs# is asserted at a rising edge of K, the internal SRAM master clock for
the following cycle is suspended, resulting in the power down of the SRAM portion
of the circuit, including the Sense Amps. CMs# can also be used to retain output
data during SRAM power-down.
Input
Input
Input
Input
Input
Input
Input
Input
K
CMd#
RAS#
CAS#
DTD#
Ad0-Ad11
CS#
CMs#
PIN DESCRIPTIONS(1)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M5M4V16169DRT-8 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
M5M4V16169DTP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
M5M4V16169DTP-10 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
M5M4V16169DTP-15 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
M5M4V16169DTP-7 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
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