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參數(shù)資料
| 型號(hào)： | M616Z08-20MH3TR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | CAT5E PATCH CORD 100 FOOT YELLOW |
| 中文描述： | 128千位8千位× 16的SRAM帶有輸出使能 |
| 文件頁(yè)數(shù)： | 6/14頁(yè) |
| 文件大?。?/td> | 95K |
| 代理商： | M616Z08-20MH3TR |
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M616Z08
6/14
Table 5. DC Characteristics
A
= –40 to 125°C; V
CC
= 3.0 to 3.6V or 2.34 to 3.0V (except where noted).
2. Input leakage on TO Pin due to internal pull-down to V
SS
.
3. Average AC current, Outputs open, cycling at t
AVAV
minimum.
4. All other Inputs at V
IL
≤
0.2V or V
IH
≥
V
CC
–0.2V.
OPERATION
READ Mode
The M616Z08 is in the READ Mode whenever
WRITE Enable (WE0 or WE1) is High with Output
Enable (OE) Low, and Chip Enable (CE) is assert-
ed. This provides access to data from sixteen of
the 131,072 locations in the static memory array,
specified by the 13 address inputs. Valid data will
be available at the sixteen output pins within t
AVQV
after the last stable address, providing OE is Low
and CE is Low. If Chip Enable or Output Enable
access times are not met, data access will be
measured from the limiting parameter (t
ELQV
or
t
GLQV
) rather than the address. Data out may be
indeterminate at t
ELQX
and t
GLQX
, but data lines
will always be valid at t
AVQV
.
Figure 5. Address Controlled, READ Mode AC Waveforms
Note: CE = Low, OE = Low, WE(0,1) = High.
Sym
Parameter
Test Condition
(1)
Min
Typ
Max
Unit
I
LI
Input Leakage Current
0V
≤
VIN
≤
V
CC
TO Pin
(2)
65
125
μA
All other inputs
±1
μA
I
LO
Output Leakage Current
0V
≤
V
OUT
≤
V
CC
±1
μA
I
CC1(3)
Supply Current
V
CC
= 3.6V
75
mA
I
CC3(4)
Supply Current (Standby)
CMOS
V
CC
= 3.6V,
CE
≥
V
CC
– 0.2V, f = 0
1
mA
V
IL
Input Low Voltage
–0.3
0.3V
CC
V
V
IH
Input High Voltage
0.7V
CC
V
CC
+ 0.3
V
V
OL
Output Low Voltage
I
OL
= 1mA
0.2
V
V
OH
Output High Voltage
I
OH
= –1mA
2.34 to 3.0V
V
CC
–0.2V
3.0 to 3.6V
V
CC
–0.3V
V
tAVAV
tAVQV
tAXQX
A0-A12
DQ0-DQ15
VALID
DATA VALID
AI04210
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