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參數(shù)資料
| 型號： | M616Z08-20MH3TR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | CAT5E PATCH CORD 100 FOOT YELLOW |
| 中文描述： | 128千位8千位× 16的SRAM帶有輸出使能 |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 95K |
| 代理商： | M616Z08-20MH3TR |
M616Z08
8/14
WRITE Mode
The M616Z08 is in the WRITE mode whenever the
WE0 (low memory addresses) or WE1 (high mem-
ory addresses) and CE pins are low (see Table 8,
page 10). Either the Chip Enable input (CE) or the
WRITE Enable input (WE0 or WE1) must be de-
asserted during Address transitions for subse-
quent WRITE cycles. WRITE begins with the con-
currence of Chip Enable being active with WE0 or
WE1 low. Therefore, address setup time is refer-
enced to WRITE Enable and Chip Enable as t
AVWL
and t
AVEH
respectively, and is determined by the
latter occurring edge.
The WRITE cycle can be terminated by the earlier
rising edge of CE, or WE0/WE1.
if the Output is enabled (CE = Low and OE = Low),
then WE0 or WE1 will return the outputs to high
impedance within t
WLQZ
of its falling edge. Care
must be taken to avoid bus contention in this type
of operation. Data input must be valid for t
DVWH
before the rising edge of WRITE Enable, or for t
D-
VEH
before the rising edge of CE, whichever oc-
curs first, and remain valid for t
WHDX
or t
EHDX
.
Note:
When using MCP555 with TO Pin high, re-
laxed WRITE timing (CSNT = 1 in the chip select
configuration register) should be selected.
Figure 7. WRITE Enable Controlled, WRITE Mode AC Waveforms
Figure 8. Chip Enable Controlled, WRITE Mode AC Waveforms
Note: 1. Output Enable (OE) = High.
2. If CE goes High with WE0 or WE1 high, the output remains in a high-impedance state.
tAVAV
tWHAX
tDVWH
DATA INPUT
A0-A12
WE (0,1)
DQ0-DQ15
CE
VALID
tAVWH
tAVEL
tWLWH
tAVWL
tWLQZ
tWHDX
tWHQX
AI04211
tAVAV
tEHAX
tDVEH
DATA INPUT
A0-A12
WE (0,1)
DQ0-DQ15
CE
VALID
tAVEH
tAVEL
tAVWL
tEHDX
tELEH
AI05639
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