Serial I/O
143
Mitsubishi microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
development
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
UARTi transmit/receive mode register (i=0 to 2)
Symbol
Address
After reset
00
16
U0MR to U2MR
03A0
16
, 03A8
16
, 0378
16
b7
b6
b5
b4
b3
b2
b1
b0
Bit name
Bit
symbol
RW
CKDIR
SMD1
SMD0
Serial I/O mode select bit
(Note 2)
SMD2
Internal/external clock
select bit
STPS
PRY
PRYE
IOPOL
Parity enable bit
0 : Internal clock
1 : External clock (Note 1)
Stop bit length select bit
Odd/even parity select bit
TxD, RxD I/O polarity
reverse bit
0 : One stop bit
1 : Two stop bits
Effective when PRYE = 1
0 : Odd parity
1 : Even parity
0 : Parity disabled
1 : Parity enabled
0 : No reverse
1 : Reverse
0 0 1 : Clock synchronous serial I/O mode
0 1 0 : I
2
C mode
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Must not be set except above
b2 b1 b0
Function
Note 1: Set the corresponding port direction bit for each CLKi pin to “0” (input mode).
Note 2: To receive data, set the corresponding port direction bit for each RxDi pin to “0” (input mode).
Note 3: Set the corresponding port direction bit for SCL and SDA pins to “0” (input mode).
UARTi transmit/receive control register 0 (i=0 to 2)
Symbol
U0C0 to U2C0
Address
After reset
03A4
16
, 03AC
16
, 037C
16
00001000
2
b7
b6
b5
b4
b3
b2
b1
b0
Function
TXEPT
CLK1
CLK0
CRS
CRD
NCH
CKPOL
BRG count source
select bit
Transmit register empty
flag
0 : Transmit data is output at falling edge of transfer clock
and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer clock
and receive data is input at falling edge
CLK polarity select bit
CTS/RTS function
select bit
(Note 4)
CTS/RTS disable bit
Data output select bit
(Note 2)
0 0 : f
1SIO
or f
2SIO
is selected
0 1 : f
8SIO
is selected
1 0 : f
32SIO
is selected
1 1 : Must not be set
b1 b0
0 : LSB first
1 : MSB first
0 : Data present in transmit register (during transmission)
1 : No data present in transmit register
(transmission completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P6
0
, P6
4
and P7
3
can be used as I/O ports)
0 : TxDi/SDAi and SCLi pins are CMOS output
1 : TxDi/SDAi and SCLi pins are N-channel open-drain output
UFORM Transfer format select bit
(Note 3)
Effective when CRD = 0
0 : CTS function is selected (Note 1)
1 : RTS function is selected
Bit name
Bit
symbol
Note 1: Set the corresponding port direction bit for each CTSi pin to “0” (input mode).
Note 2: T
X
D
2
/SDA
2
and SCL
2
are N-channel open-drain output. Cannot be set to the CMOS output. Set the NCH bit of the U2C0
register to “0”.
Note 3: Effective for clock synchronous serial I/O mode and UART mode transfer data 8 bits long.
Note 4: CTS
1
/RTS
1
can be used when the UCON register’s CLKMD1 bit = “0” (only CLK
1
output) and the UCON register’s RCSP bit =
“0” (CTS
0
/RTS
0
not separated).
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
(Note 3)
Figure 1.17.4. U0MR to U2MR Register and U0C0 to U2C0 Register