186
Mitsubishi microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
development
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
SI/O3, SI/O4
Item
Specification
Transfer data format
Transfer clock
Transfer data length: 8 bits
SiC (i=3, 4) register’s SMi6 bit = “1” (internal clock) : fj/ 2(n+1)
fj = f
1SIO
, f
8SIO
, f
32SIO
. n=Setting value of SiBRG register 00
16
to FF
16
.
SMi6 bit = “0” (external clock) : Input from CLKi pin (Note 1)
Before transmission/reception can start, the following requirements must be met
Write transmit data to the SiTRR register (Notes 2, 3)
When SiC register's SMi4 bit = 0
The rising edge of the last transfer clock pulse (Note 4)
When SMi4 = 1
The falling edge of the last transfer clock pulse (Note 4)
I/O port, transfer clock input, transfer clock output
I/O port, transmit data output, high-impedance
I/O port, receive data input
LSB first or MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
Function for setting an S
OUT
i initial value set function
When the SiC register's SMi6 bit = 0 (external clock), the S
OUT
i pin output level while
not tranmitting can be selected.
CLK polarity selection
Whether transmit data is output/input timing at the rising edge or falling edge of
transfer clock can be selected.
Note 1: To set the SiC register’s SMi6 bit to “0” (external clock), follow the procedure described below.
If the SiC register’s SMi4 bit = 0, write transmit data to the SiTRR register while input on the CLKi pin is
high. The same applies when rewriting the SiC register’s SMi7 bit.
If the SMi4 bit = 1, write transmit data to the SiTRR register while input on the CLKi pin is low. The same
applies when rewriting the SMi7 bit.
Because shift operation continues as long as the transfer clock is supplied to the SI/Oi circuit, stop the
transfer clock after supplying eight pulses. If the SMi6 bit = 1 (internal clock), the transfer clock automatically
stops.
Note 2: Unlike UART0 to UART2, SI/Oi (i = 3 to 4) is not separated between the transfer register and buffer. There-
fore, do not write the next transmit data to the SiTRR register during transmission.
Note 3: When the SiC register’s SMi6 bit = 1 (internal clock), S
OUTi
retains the last data for a 1/2 transfer clock period
after completion of transfer and, thereafter, goes to a high-impedance state. However, if transmit data is
written to the SiTRR register during this period, S
OUTi
immediately goes to a high-impedance state, with the
data hold time thereby reduced.
Note 4: When the SiC register’s SMi6 bit = 1 (internal clock), the transfer clock stops in the high state if the SMi4 bit
= 0, or stops in the low state if the SMi4 bit = 1.
Transmission/reception
start condition
Interrupt request
generation timing
CLKi pin fucntion
S
OUT
i pin function
SINi pin function
Select function
Table 1.21.1. SI/O3 and SI/O4 Specifications