A-D Converter
205
Mitsubishi microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
development
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Microcomputer
Note 1: C1
≥
0.47
μ
F, C2
≥
0.47
μ
F, C3
≥
100pF, C4
≥
0.1
μ
F, C5
≥
0.1
μ
F (reference)
Note 2: Use thick and shortest possible wiring to connect capacitors.
V
CC1
V
SS
AV
CC
AV
SS
V
REF
ANi
C4
C1
C2
C3
V
CC2
V
SS
C5
ANi: ANi, AN
0
i, and AN
2
i (i=0 to 7)
(g) Caution of Using A-D Converter
(1) Make sure the port direction bits for those pins that are used as analog inputs are set to “0” (input
mode). Also, if the ADCON0 register’s TGR bit = 1 (external trigger), make sure the port direction bit
for the AD
TRG
pin is set to “0” (input mode).
(2) When using key input interrupts, do not use any of the four AN
4
to AN
7
pins as analog inputs. (A key
input interrupt request is generated when the A-D input voltage goes low.)
(3) To prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert
capacitors between the AV
CC
, V
REF
, and analog input pins (ANi (i=0 to 7), AN
0
i, and AN
2
i) each and
the AV
SS
pin. Similarly, insert a capacitor between the V
CC
pin and the V
SS
pin. Figure 1.22.11 is an
example connection of each pin.
(4) If V
CC2
< V
CC1
, do not use AN
00
to AN
07
and AN
20
to AN
27
as analog input pins.
(5) If the CPU reads the ADi register (i = 0 to 7) at the same time the conversion result is stored in the ADi
register after completion of A-D conversion, an incorrect value may be stored in the ADi register. This
problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for
CPU clock.
When operating in one-shot or single-sweep mode
Check to see that A-D conversion is completed before reading the target ADi register. (Check the IR
bit in the ADIC register to see if A-D conversion is completed.)
When operating in repeat mode or repeat sweep mode 0 or 1
Use the main clock for CPU clock directly without dividing it.
(6) If A-D conversion is forcibly terminated while in progress by setting the ADCON0 register’s ADST bit
to “0” (A-D conversion halted), the conversion result of the A-D converter is indeterminate. The con-
tents of ADi registers irrelevant to A-D conversion may also become indeterminate. If while A-D con-
version is underway the ADST bit is cleared to “0” in a program, ignore the values of all ADi registers.
Figure 1.22.11. V
CC
, V
SS
, AV
CC
, AV
SS
, V
REF
and ANi Connection