2
MITSUBISHI
DIGITAL ASSP
M66238FP
STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER
PIN DESCRIPTIONS
Pin name
RESET
CS
SIN
SCLK
Name
Reset input
Chip select input
Serial data input
Serial clock input
Clock input
Clock output
Trigger input
Clock output
PLL output
One-shot pulse output
Filter connect pin
Filter connect pin
VCO load output
Test pin
Test pin
Test pin
Test pin
Digital power supply pin
Digital GND pin
Sync output power supply pin
Sync output GND pin
Analog power supply pin
Analog GND pin
XIN
XOUT
TR
CKOB
CKO/PLLO
PULSE
CPOUT
CPIN
RV
TCKI
TCKO
UP
DOWN
DVCC
DGND
VCCO
GNDO
AVCC
AGND
I/O
Input
Input
Input
Input
Input
Output
Input
Output
Output
Output
Output
Input
Output
Input
Output
Output
Output
—
—
—
—
—
—
Function
Initialize M66238 internal status.
Transfer serial data when CS=“L”.
Synchronize 32-bit serial data from MCU with SCK, and enter.
Enter a sync clock for writing 32-bit serial data.
Used by connecting crystal oscillator between XIN and XOUT. When using an
external clock signal, connect the clock oscillator to XIN pin and open XOUT pin.
Trigger input for clock sync.
Output an inverted CKO signal.
CKO outputs a clock synchronized with a trigger signal and PLLO outputs a PLL
oscillator clock as it is.
Output a one-shot pulse synchronized with a CKO signal.
Connect a low pass filter to charge pump output.
Low pass filter input pin.
Connect a load resistor for VCO circuit operation between RV and GND.
Shipping test pin. Connect to GND when use.
Shipping test pin. Keep open when use.
Shipping test pin. Keep open when use.
Shipping test pin. Keep open when use.
Digital power supply pin.
Digital GND pin.
Power supply pin for sync output.
GND pin for sync output.
Analog power supply pin.
Analog GND pin.
LIST OF REGISTER SETTING COMMANDS
A1
A0
0
1
1
0
0
1
Setting
Setting of CKO/PLLO dividing ratio,
PLL synthesizer 15-bit generation
dividing ratio and reference clock
generation 12-bit dividing ratio.
Setting of one-shot pulse polarity and
width, setting of trigger edge, HALT of
entire M66238, HALT of charge pump
and VCO, phase comparator output
UP/DOWN, CKO/PLLO switching.
Dummy trigger generation command
SERIAL DATA WRITE TIMING
A0
A1
D0
D1
D2
D3
D4
D5
D6
D26
D27
D28
D29
CS
SCLK
SIN
Address bit
Data bit