參數(shù)資料
型號(hào): M66238FP
廠商: Mitsubishi Electric Corporation
英文描述: STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER
中文描述: 標(biāo)準(zhǔn)時(shí)鐘發(fā)生器,鎖相環(huán)頻率合成器
文件頁(yè)數(shù): 3/11頁(yè)
文件大?。?/td> 102K
代理商: M66238FP
3
MITSUBISHI
DIGITAL ASSP
M66238FP
STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER
REGISTER CONFIGURATION
1. Clock frequency setting command
Reference clock generation 12-bit division ratio, PLL synthe-
sizer 15-bit division ratio and CKO/PLLO division ratio are set
at address (A1, A0) = (0, 0).
Data bit
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
Default
0
1
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
0
1
0
Description
12-bit reference clock dividing ratio is set.
D11 and D0 correspond to MSB and LSB, respectively.
11
K =
(D
k
×
2
k
)
k = 0
K: Reference clock dividing ratio
15-bit PLL synthesizer dividing ratio is set.
D26 and D12 correspond to MSB and LSB, respectively.
26
N =
(D
n
×
2
n–12
)
n = 12
N: PLL synthesizer dividing ratio
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Setting of CKO/PLLO dividing ratios
Dividing ratio
1/1
1/2
1/4
1/8
1/16
1/32
D29
0
0
0
0
1
1
D28
0
0
1
1
0
0
D27
0
1
0
1
0
1
PLLO/CKO oscillator frequency
25MHz ~ 50MHz
12.5MHz ~ 25MHz
6.25MHz ~ 12.5MHz
3.125MHz ~ 6.25MHz
1.563MHz ~ 3.125MHz
0.781MHz ~ 1.563MHz
Remarks
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