參數(shù)資料
型號: M66238FP
廠商: Mitsubishi Electric Corporation
英文描述: STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER
中文描述: 標(biāo)準(zhǔn)時鐘發(fā)生器,鎖相環(huán)頻率合成器
文件頁數(shù): 5/11頁
文件大?。?/td> 102K
代理商: M66238FP
5
MITSUBISHI
DIGITAL ASSP
M66238FP
STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER
3. Dummy trigger generating command
The internal status of sync clock generator becomes un-
stable and a stable sync clock output (CKO) is not obtained
after the power is turned on, after a reset is cleared or after
an internal VCO oscillator frequency is set. To obtain a stable
sync clock output, enter a trigger signal from the TR input af-
ter VCO oscillator becomes stable, or enter a dummy trigger
generating command from the MCU. The PLL synthesizer
oscillator frequency after the cancellation of a reset depends
on a default (See the register configuration).
Set the command for address (A1, A0) = (1, 1).
Description
The command must be stored two times continuously when a dummy trigger is generated.
For the first time, set the dummy trigger generating command with D0=1.
For the second time, set the dummy trigger generating command with D0=0.
The second setting becomes a sync edge and a clock begins to be output from CKO.
After the first setting, CKO is in the halt state.
In normal use: “0”
0
1
0
1
0
1
Data bit
D0
D1
D29
Default
0
0
0
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