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參數(shù)資料
| 型號： | M66257 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 5120 x 8-BIT x 2 LINE MEMORY (FIFO) |
| 中文描述： | 5120 × 8位× 2列內(nèi)存（先進先出） |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 122K |
| 代理商： | M66257 |
2
MITSUBISHI
DIGITAL ASSP
M66257FP
5120
×
8-BIT
×
2 LINE MEMORY (FIFO)
FUNCTION
When write enable input WE is “L”, the contents of data inputs
D
0
to D
7
are written into 1-line delay data only memory in syn-
chronization with rise edge of write clock input WCK. At this
time, the write address counter of 1-line delay data only
memory is also incremented simultaneously.
The write functions given below are also performed in syn-
chronization with rise edge of WCK.
When WE is “H”, a write operation to 1-line delay data only
memory is inhibited and the write address counter of 1-line
delay data only memory is stopped.
When write reset input WRES is “L”, the write address counter
of 1-line delay data only memory is initialized.
When read enable input RE is “L”, the contents of 1-line delay
data only memory are output to data outputs Q
00
to Q
07
and
those of 2-line delay data only memory to data outputs Q
10
to
Q
17
in synchronization with the rise of read clock input RCK.
At this time, the read address counters of 1-line and 2-line
delay data only memories is also incremented simulta-
neously.
Moreover, data of Q
00
to Q
07
are written into 2-line delay data
only memory in synchronization with rise edge of RCK. At
this time, the write address of 2-line delay data only memory
is incremented.
The read functions given below are also performed in syn-
chronization with rise edge of RCK.
When RE is “H”, a read operation from both of 1-line delay
data only memory and 2-line delay data only memory is inhib-
ited and the read address counter of each memory is
stopped. The outputs of Q
00
to Q
07
and Q
10
to Q
17
are in the
high impedance state.
Moreover, a write operation to 2-line delay data only memory
is inhibited and the write address counter of 2-line delay data
only memory is stopped.
When read reset input RRES is “L”, the read address counter
of 1-line delay data only memory, and the write address
counter and read address counter of 2-line delay data only
memory are initialized.
相關PDF資料 |
PDF描述 |
|---|---|
| M66257FP | 5120 x 8-BIT x 2 LINE MEMORY (FIFO) |
| M66258 | 8192 x 8-BIT LINE MEMORY |
| M66258FP | 8192 x 8-BIT LINE MEMORY |
| M66260FP | 8 x 4 CROSSPOINT SWITCH with MIXING FUNCTION |
| M66261FP | 6 x 5 CROSSPOINT SWITCH with MIXING FUNCTION |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M66257FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:5120 x 8-BIT x 2 LINE MEMORY (FIFO) |
| M66258 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:8192 x 8-BIT LINE MEMORY |
| M66258FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:8192 x 8-BIT LINE MEMORY |
| M66258FP(#TF0T) | 制造商:Renesas Electronics Corporation 功能描述: |
| M66260FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:8 x 4 CROSSPOINT SWITCH with MIXING FUNCTION |
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