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參數(shù)資料
| 型號(hào)： | M68AR256ML70ZB1F |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | SRAM |
| 英文描述： | 256K X 16 STANDARD SRAM, 70 ns, PBGA48 |
| 封裝： | 6 X 7 MM, 0.75 MM PITCH, LEAD FREE, TFBGA-48 |
| 文件頁數(shù)： | 5/21頁 |
| 文件大?。?/td> | 414K |
| 代理商： | M68AR256ML70ZB1F |
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M68AR256M
Table 7. Read and Standby Mode AC Characteristics
Note: 1. Test conditions assume transition timing reference level = 0.3VCC or 0.7VCC.
2. At any given temperature and voltage condition, tGHQZ is less than tGLQX, tBHQZ is less than tBLQX and tEHQZ is less than tELQX for
any given device.
3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
4.Tested initially and after any design or process changes that may affect these parameters.
Symbol
Parameter
M68AR256M
Unit
55
70
tAVAV
Read Cycle Time
Min
55
70
ns
tAVQV
Address Valid to Output Valid
Max
55
70
ns
tAXQX
(1)
Data hold from address change
Min
5
ns
tBHQZ
(2,3)
Upper/Lower Byte Enable High to Output Hi-Z
Max
20
25
ns
tBLQV
Upper/Lower Byte Enable Low to Output Valid
Max
55
70
ns
tBLQX
(1)
Upper/Lower Byte Enable Low to Output Transition
Min
5
ns
tEHQZ
(2,3)
Chip Enable High to Output Hi-Z
Max
20
25
ns
tELQV
Chip Enable Low to Output Valid
Max
55
70
ns
tELQX
(1)
Chip Enable Low to Output Transition
Min
5
ns
tGHQZ
(2,3)
Output Enable High to Output Hi-Z
Max
20
25
ns
tGLQV
Output Enable Low to Output Valid
Max
25
35
ns
tGLQX
(2)
Output Enable Low to Output Transition
Min
5
ns
tPD
(4)
Chip Enable or UB/LB High to Power Down
Max
55
70
ns
tPU
(4)
Chip Enable or UB/LB Low to Power Up
Min
0
ns
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