參數(shù)資料
型號(hào): M68AR256ML70ZB1F
廠商: STMICROELECTRONICS
元件分類: SRAM
英文描述: 256K X 16 STANDARD SRAM, 70 ns, PBGA48
封裝: 6 X 7 MM, 0.75 MM PITCH, LEAD FREE, TFBGA-48
文件頁數(shù): 8/21頁
文件大小: 414K
代理商: M68AR256ML70ZB1F
Obsolete
Product(s)
- Obsolete
Product(s)
Obsolete
Product(s)
- Obsolete
Product(s)
M68AR256M
16/21
Table 8. Write Mode AC Characteristics
Note: 1. At any given temperature and voltage condition, tWLQZ is less than tWHQX for any given device.
2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
Symbol
Parameter
M68AR256M
Unit
-L
-N
55
70
55
70
tAVAV
Write Cycle Time
Min
557055
70
ns
tAVBH
Address Valid to LB, UB High
Min
456045
60
ns
tAVBL
Addess Valid to LB, UB Low
Min
0
000
ns
tAVEH
Address Valid to Chip Enable High
Min
45
60
45
60
ns
tAVEL
Address valid to Chip Enable Low
Min
0
ns
tAVWH
Address Valid to Write Enable High
Min
45
60
45
60
ns
tAVWL
Address Valid to Write Enable Low
Min
0
ns
tBHAX
LB, UB High to Address Transition
Min
0
ns
tBHDX
LB, UB High to Input Transition
Min
0
ns
tBLBH
LB, UB Low to LB, UB High
Min
45
60
45
60
ns
tBLEH
LB, UB Low to Chip Enable High
Min
45
60
45
60
ns
tBLWH
LB, UB Low to Write Enable High
Min
45
60
45
60
ns
tDVBH
Input Valid to LB, UB High
Min
253025
30
ns
tDVEH
Input Valid to Chip Enable High
Min
25
30
25
30
ns
tDVWH
Input Valid to Write Enable High
Min
25
30
25
30
ns
tEHAX
Chip Enable High to Address Transition
Min
0
ns
tEHDX
Chip enable High to Input Transition
Min
0
ns
tELBH
Chip Enable Low to LB, UB High
Min
45
60
45
60
ns
tELEH
Chip Enable Low to Chip Enable High
Min
45
60
45
60
ns
tELWH
Chip Enable Low to Write Enable High
Min
45
60
45
60
ns
tWHAX
Write Enable High to Address Transition
Min
0
ns
tWHDX
Write Enable High to Input Transition
Min
0
ns
tWHQX
(1)
Write Enable High to Output Transition
Min
5
ns
tWLBH
Write Enable Low to LB, UB High
Min
456045
60
ns
tWLEH
Write Enable Low to Chip Enable High
Min
45
60
45
60
ns
tWLQZ
(1,2)
Write Enable Low to Output Hi-Z
Max
20
ns
tWLWH
Write Enable Low to Write Enable High
Min
45
60
40
50
ns
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