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參數(shù)資料
| 型號(hào)： | M68AR256ML70ZB1F |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | SRAM |
| 英文描述： | 256K X 16 STANDARD SRAM, 70 ns, PBGA48 |
| 封裝： | 6 X 7 MM, 0.75 MM PITCH, LEAD FREE, TFBGA-48 |
| 文件頁(yè)數(shù)： | 9/21頁(yè) |
| 文件大?。?/td> | 414K |
| 代理商： | M68AR256ML70ZB1F |
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M68AR256M
Figure 13. Low VCC Data Retention AC Waveforms
Table 9. Low VCC Data Retention Characteristics
Note: 1. All other Inputs at VIH ≥ VCC –0.2V or VIL ≤ 0.2V.
2. Tested initially and after any design or process changes that may affect these parameters. tAVAV is Read cycle time.
3. No input may exceed VCC +0.2V.
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
ICCDR
(1)
Supply Current (Data Retention)
VCC = 1.0V, E ≥ VCC –0.2V or
UB = LB
≥ VCC –0.2V, f = 0 (3)
0.5
3
A
tCDR
(1,2)
Chip Deselected to Data
Retention Time
0ns
tR
(2)
Operation Recovery Time
tAVAV
ns
VDR
(1)
Supply Voltage (Data Retention)
E
≥ VCC –0.2V or
UB = LB
≥ VCC –0.2V, f = 0
1.0
V
AI03859
DATA RETENTION MODE
tR
1.95V
tCDR
VCC
1.65V
VDR > 1.0V
E or UB/LB
E
≥ VDR – 0.2V or UB = LB ≥ VDR – 0.2V
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