參數(shù)資料
型號: M69AW048BL70ZB8
廠商: 意法半導(dǎo)體
英文描述: 32 Mbit (2M x16) 3V Asynchronous PSRAM
中文描述: 32兆位(200萬× 16)3V的異步移動存儲芯片
文件頁數(shù): 24/29頁
文件大?。?/td> 433K
代理商: M69AW048BL70ZB8
M69AW048B
24/29
Table 13. Standby/Power-Down Mode AC Characteristics
Note: 1. Applicable also to Power-up.
2. Applicable when 4Mb, 8Mb and 16Mb PAR mode is programmed
3. Some data might be written into any address location if t
EHWL
(min) is not satisfied.
4. The Input Transition Time (t
τ
) at AC testing is 5ns as shown below. If actual t
τ
is longer than 5ns, it may violate AC specification of
some timing parameters.
Figure 22. Power Down Program AC Waveforms
Note: 1. E2 = High.
2. All address inputs must be High from Cycle 1 to Cycle 5.
3. PDCADD stands for Power-Down Configuration Address. It must be compliant with the format specified in Table
6
otherwise the
data programmed during the Power-Down Program sequence may be incorrect.
4. PDCDAT stands for Power-Down Configuration Data. It must be compliant with the format specified in Table
5
otherwise the data
programmed during the Power-Down Program sequence may be incorrect.
5. t
EHEL
after the end of Cycle 6, the Power Down Program is completed and the device returns to normal operation.
Symbol
Alt.
Parameter
M69AW048B
Unit
Min
Max
t
CLEX
t
CSP
E2 Low Setup Time for Power Down Entry
10
ns
t
EXCH
t
C2LP
E2 Low Hold Time after Power Down Entry
70
ns
t
EHEV (1)
t
CHH
E1 High Hold Time following E2 High after Power-
Down Exit (Deep Power-Down Mode only)
300
μs
t
CHEL (2)
t
CHHP
E1 High Hold Time following E2 High after Power-
Down Exit (not in Deep Power-Down Mode)
1
μs
t
EHCH
t
CHS
E1 High Setup Time following E2 High after Power-
Down Exit
0
μs
t
EHGL
t
CHOX
E1 High to G Invalid Time for Standby Entry
10
ns
t
EHWL (3)
t
CHWX
E1 High to W Invalid Time for Standby Entry
10
ns
t
τ
(4)
t
τ
Input Transition Time
1
25
ns
AI07225c
A0-A20
E1
W
DQ0-DQ15
MSB 2
G
MSB 2
MSB 2
MSB 2
MSB 2
PDCADD3
LB, UB
tAXAV
tAXAVL
4
tAVAX
RDa
RDa
RDa
00
PDCD
4
RDb
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
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