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參數資料
| 型號： | M7010R-083ZA1T |
| 廠商： | 意法半導體 |
| 英文描述： | 16K x 68-bit Entry NETWORK SEARCH ENGINE |
| 中文描述： | 16K的× 68位進入網絡搜索引擎 |
| 文件頁數： | 20/67頁 |
| 文件大?。?/td> | 449K |
| 代理商： | M7010R-083ZA1T |
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M7010R
20/67
The Command Register
Table 10. Command Register Field Descriptions
Field
Range
Initial Value
Description
SRST
[0]
0
Software Reset.
If '1,' this bit resets the device, with the same effect as the
hardware reset. Internally, it generates a reset pulse lasting for eight CLK
cycles. This bit automatically resets to a '0' during the reset cycle.
DEVE
[1]
0
Device Enable.
If '0,' it keeps the SRAM bus (SADR, WE_L, CE_L, OE_L,
and ALE_L), SSF, and SSV signals in a tri-state condition and forces the
cascade interface output signals LHO[1:0] and BHO[2:0] to '0.' It also keeps
the DQ Bus in Input mode. The purpose of this bit is to make sure that there
is no bus contention when the devices power-up in the system.
TLSZ
[3:2]
01
Table Size.
The host ASIC must program this field to configure the chips into
a table of a certain size. This field affects the pipeline latency of the SEARCH
and LEARN operations as well as the READ and WRITE accesses to the
SRAM (SADR[21:0], CE_L, OE_L, WE_L, ALE_L, SSV, SSF, and ACK).
Once programmed, the SEARCH latency stays constant.
Latency #
CLK Cycles
00: 1 device
4
01: 2-8 devices
5
10: 9-31
devices
6
11: Reserved
HLAT
[6:4]
000
Latency of Hit Signals.
This field adds latency to the SSF, SSV, and ACK
signals by the following number of CLK cycles during SEARCH and ACK
during an SRAM READ access.
000: 0
100: 4
001: 1
101: 5
010: 2
110: 6
011: 3
111: 7
LDEV
[7]
0
Last device in the cascade.
When set, this device is the last device in the
depth-cascaded table and is the default driver for the SSF and SSV signals.
In the event of a SEARCH failure, the device with this bit set drives the hit
signals as follows:
SSF = 0, SSV = 1
During non-search cycles, the device with this bit set drives the signals as
follows:
SSF = 0, SSV = 0
LRAM
[8]
0
Last device on this SRAM Bus.
When set, this device is the last device on
the SRAM bus in the depth-cascaded table and is the default driver for the
SADR, CE_L, WE_L, and ALE_L signals. In cycles where no M7010R
device (in a depth-cascaded table) drives these signals, the signals are
driven as follows:
SADR = 22
’
h3FFFFF, CE_L = 1, WE_L = 1, and ALE_L = 1.
OE_L is always driven by the device for which this bit is set.
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