參數(shù)資料
型號(hào): M7010R-083ZA1T
廠商: 意法半導(dǎo)體
英文描述: 16K x 68-bit Entry NETWORK SEARCH ENGINE
中文描述: 16K的× 68位進(jìn)入網(wǎng)絡(luò)搜索引擎
文件頁數(shù): 30/67頁
文件大?。?/td> 449K
代理商: M7010R-083ZA1T
M7010R
30/67
Table 18. READ Command Parameters
Table 19. Data and Mask Array, SRAM READ Address Format
Note: 1.
|
stands for logical OR operation, and
{ }
stands for concatenation operator.
Table 20. READ Address Format for Internal Registers
CMD Parameter
CMD[2]
Read Command
Description
0
Single Read
Reads a single location of the data array, mask array, external SRAM,
or device registers. All access information is applied on the DQ Bus.
1
Burst Read
Reads a block of locations from the data array or mask array as a
burst.
The internal register (RBURADR) specifies the starting address and
the length of the data transfer from the data array or mask array, and it
auto-increments the address for each access.
All other access information is applied on the DQ Bus.
Note:
The device registers and external SRAM can only be read in
single-read mode.
DQ
[67:30]
DQ
[29]
DQ
[28:26]
DQ
[25:21]
DQ
[20:19]
DQ
[18:14]
DQ
[13:0]
Reserved
0: Direct
1: Indirect
SuccessfulSEARCH
Register Index
(Applicableif DQ[29]
is indirect)
ID
00: Data
Array
Reserved
If DQ[29] is '0,' this field carries
address of data array location.
If DQ[29] is '1,' the successful
SEARCH Register specified on
DQ[28:26] supplies the address
of the data array location:
{SSR[13:2], SSR[1] | DQ[1],
SSR[0] | DQ[0]}
(1)
Reserved
0: Direct
1: Indirect
SuccessfulSEARCH
Register Index
(Applicableif DQ[29]
is indirect)
ID
01: Mask
Array
Reserved
If DQ[29] is '0,' this field carries
address of mask array location.
If DQ[29] is '1,' the successful
SEARCH Register specified on
DQ[28:26] supplies the address
of the mask array location:
{SSR[13:2], SSR[1] | DQ[1],
SSR[0] | DQ[0]}
(1)
Reserved
0: Direct
1: Indirect
SuccessfulSEARCH
Register Index
(Applicableif DQ[29]
is indirect)
ID
10:
External
SRAM
Reserved
If DQ[29] is '0,' this field carries
address of SRAM location.
If DQ[29] is '1,' the successful
SEARCH Register specified on
DQ[28:26] supplies the address
of the SRAM location.
DQ[67:26]
DQ[25:21]
DQ[20:19]
DQ[18:6]
DQ[5:0]
Reserved
ID
11: Register
Reserved
Register Address
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