參數(shù)資料
型號(hào)： M7010R-083ZA1T
廠商： 意法半導(dǎo)體
英文描述： 16K x 68-bit Entry NETWORK SEARCH ENGINE
中文描述： 16K的× 68位進(jìn)入網(wǎng)絡(luò)搜索引擎
文件頁(yè)數(shù)： 58/67頁(yè)
文件大?。?/td> 449K
代理商： M7010R-083ZA1T
M7010R
58/67
SRAM ADDRESSING
Table 35, page 61 lists and describes the com-
mands used to generate addresses on the SRAM
address bus. The Index[13:0] field contains the ad-
dress of a 68-bit entry that results in a hit in 68-bit
configured quadrant. It is the address of the 68-bit
entry that lies at the 136-bit page and 272-bit page
boundaries in 136-bit and 272-bit configured
quadrants, respectively.
The register section of this specification describes
the NFA and SSR registers. Adr[13:0] contains the
address supplied on the DQ Bus during PIO ac-
cess to the M7010R. Command Bits 8 and 7,
CMD[8:6] are passed from the command to the
SRAM address bus. See COMMAND CODES
AND PARAMETERS, page 27 for more informa-
tion.
SRAM PIO Access
SRAM READ.
Enables READ access to the off-
chip SRAM that contains associative data. The la-
tency from the issuance of the READ Instruction to
the address appearing on the SRAM bus is the
same as the latency of the SEARCH Instruction,
and will depend on the value programmed for the
TLSZ parameter in the device configuration regis-
ter. The latency of the ACK from the READ In-
struction is the same as the latency of the
SEARCH Instruction to the SRAM address plus
the HLAT programmed into the configuration reg-
ister.
Note:
SRAM READ is a blocking operation - no
new instruction can begin until the ACK is returned
by the selected device performing the access.
The following explains the SRAM READ operation
in a table with only one device and having the fol-
lowing parameters: TLSZ = 00, HLAT = 000,
LRAM = 1, and LDEV = 1. Figure 43, page 59
shows the associated timing diagram. For the fol-
lowing description, the selected device refers only
to the device in the table because it is the only de-
vice to be accessed.
–
Cycle 1A:
The host ASIC applies the READ In-
struction on CMD[1:0] using CMDV = 1. The DQ
Bus supplies the address, with DQ[20:19] set to
“
10,
”
to select the SRAM address. The host
ASIC selects the device for which the ID[4:0]
matches the DQ[25:21] lines. During this cycle,
the host ASIC also supplies SADR[21:19] on
CMD[8:6].
–
Cycle 1B:
The host ASIC continues to apply the
READ Instruction on CMD[1:0] using CMDV =
1. The DQ Bus supplies the address with
DQ[20:19] set to
“
10
”
to select the SRAM ad-
dress.
–
Cycle 2:
The host ASIC floats DQ[67:0] to a tri-
state condition.
–
Cycle 3:
The host ASIC keeps DQ[67:0] in a tri-
state condition.
–
Cycle 4:
The selected device starts to drive
DQ[67:0] and drives ACK from High-Z to LOW.
–
Cycle 5:
The selected device drives the READ
address on SADR[21:0]; it also drives ACK
HIGH, CE_L LOW, and ALE_L LOW.
–
Cycle 6:
The selected device drives CE_L
HIGH, ALE_L HIGH, the SADR Bus and DQ
Bus in a tri-state condition, and ACK LOW.
At the end of Cycle 6, the selected device floats
ACK in a tri-state condition, and a new command
can begin. Table 36, page 62 shows by how many
cycles SRAM signals shift to the right for various
TLSZ values. Table 37, page 62 shows by how
many cycles SRAM signals shift to the right for
various HLAT values.
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