參數(shù)資料
型號(hào)： M7010R
廠商： 意法半導(dǎo)體
英文描述： 16K x 68-bit Entry NETWORK SEARCH ENGINE
中文描述： 16K的× 68位進(jìn)入網(wǎng)絡(luò)搜索引擎
文件頁數(shù)： 33/67頁
文件大?。?/td> 449K
代理商： M7010R
33/67
M7010R
Table 22. (Single) WRITE Address Format for Data and Mask Arrays or SRAM
Note: 1.
“
|
”
stands for logical OR operation, and
“
{ }
”
stands for concatenation operator.
Table 23. WRITE Address Format for Internal Registers
Table 24. WRITE Address Format for Data and Mask Array (Burst WRITE)
DQ
[67:30]
DQ
[29]
DQ
[28:26]
DQ
[25:21]
DQ
[20:19]
DQ
[18:14]
DQ
[13:0]
Reserved
0: Direct
1: Indirect
Successful
SEARCH
Register Index
(Applicable if
DQ[29] is
indirect)
ID
00: Data
Array
Reserved
If DQ[29] is '0,' this field carries the
address of the data array location.
If DQ[29] is '1,' the SSR specified on
DQ[28:26] is used to generate the
address of the data array location:
{SSR[13:2], SSR[1] | DQ[1], SSR[0]
| DQ[0]}.
(1)
Reserved
0: Direct
1: Indirect
Successful
SEARCH
Register Index
(Applicable if
DQ[29] is
indirect)
ID
01: Mask
Array
Reserved
If DQ[29] is '0,' this field carries
address of the mask array location.
If DQ[29] is '1,' the SSR specified on
DQ[28:26] is used to generate the
address of the data array location:
{SSR[13:2], SSR[1] | DQ[1], SSR[0]
| DQ[0]}.
(1)
Reserved
0: Direct
1: Indirect
Successful
SEARCH
Register Index
(Applicable if
DQ[29] is
indirect)
ID
10:External
SRAM
Reserved
If DQ[29] is '0,' this field carries
address of the data SRAM location.
If DQ[29] is '1,' the SSR specified on
DQ[28:26] is used to generate the
address of the data array location:
{SSR[13:2], SSR[1] | DQ[1], SSR[0]
| DQ[0]}.
(1)
DQ[67:26]
DQ[25:21]
DQ[20:19]
DQ[18:6]
DQ[5:0]
Reserved
ID
11: Register
Reserved
Register address
DQ
[67:26]
DQ
[25:21]
DQ
[20:19]
DQ
[18:14]
DQ
[13:0]
Reserved
ID
00: Data array
Reserved
Don
’
t care. These 14 bits come from the
internal register (WBURADR), which
increments with each access.
Reserved
ID
01: Mask array
Reserved
Don
’
t care. These 14 bits come from the
internal register (WBURADR), which
increments with each access.
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