參數(shù)資料
型號(hào)： M7040N
廠商： 意法半導(dǎo)體
英文描述： 64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE
中文描述： 64K的× 72位的網(wǎng)絡(luò)數(shù)據(jù)包進(jìn)入搜索引擎
文件頁(yè)數(shù)： 102/159頁(yè)
文件大小： 1088K
代理商： M7040N
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M7040N
102/159
The following is the sequence of operation for a
single 288-bit SEARCH command (see COM-
MAND CODES AND PARAMETERS, page 30).
–
Cycle A:
The host ASIC drives the CMDV high
and applies SEARCH command code ('10') on
CMD[1:0] signals. {CMD[10],CMD[5:3]} signals
must be driven with the index to the GMR pair
used for bits [287:144] of the data being
searched. DQ[71:0] must be driven with the 72-
bit data ([287:216])to be compared to all loca-
tions
“
0
”
in the four 72-bit-word page. The
CMD[2] signal must be driven to logic '1.'
Note:
CMD[2] = 1 signals that the search is a
x288-bit search. CMD[8:6] is ignored in this cy-
cle.
–
Cycle B:
The host ASIC continues to drive the
CMDV high and applies SEARCH command
('10') on CMD[1:0]. The DQ[71:0] is driven with
the 72-bit data ([215:144]) to be compared to all
locations '1' in the four 72-bits-word page.
–
Cycle C:
The host ASIC drives the CMDV high
and applies SEARCH command code ('10') on
CMD[1:0] signals. {CMD[10],CMD[5:3]} signals
must be driven with the index to the GMR pair
used for the bits [143:0] of the data being
searched. CMD[8:6] signals must be driven with
the bits that will be driven by this device on
SADR[23:21] if it has a hit. DQ[71:0] must be
driven with the 72-bit data ([143:72]) to be com-
pared to all locations
“
2
”
in the four 72-bit-word
page. The CMD[2] signal must be driven to logic
'0.'
–
Cycle D:
The host ASIC continues to drive the
CMDV high and continues to apply SEARCH
command code ('10') on CMD[1:0]. CMD[8:6]
signals must be driven with the index of the SSR
that will be used for storing the address of the
matching entry and the Hit Flag (see SEARCH-
Successful Registers (SSR[0:7]), page 24). The
DQ[71:0] is driven with the 72-bit data ([71:0]) to
be compared to all locations
“
3
”
in the four 72-
bit-word page. CMD[5:2] is ignored because the
LEARN Instruction is not supported for x288 ta-
bles.
Note:
For 288-bit searches, the host ASIC must
supply four distinct 72-bit data words on
DQ[71:0] during Cycles A, B, C, and D. The
GMR Index in Cycle A selects a pair of GMRs in
each of the 31 devices that apply to DQ data in
Cycles A and B. The GMR Index in Cycle C se-
lects a pair of GMRs in each of the 31 devices
that apply to DQ data in Cycles C and D.
The logical 288-bit SEARCH operation is as
shown in Figure 76, page 105. The entire table of
288-bit entries is compared to a 288-bit word K
that is presented on the DQ Bus in Cycles A, B, C,
and D of the command using the GMR and local
mask bits. The GMR is the 288-bit word specified
by the two pairs of GMRs selected by the GMR In-
dexes in the command
’
s Cycles A and C in each
of the 31 devices. The 288-bit word K that is pre-
sented on the DQ Bus in Cycles A, B, C, and D of
the command is compared to each entry in the ta-
ble starting at location
“
0.
”
The first matching en-
try
’
s location address,
“
L,
”
is the winning address
that is driven as part of the SRAM address on the
SADR[23:0] lines (see SRAM ADDRESSING,
page 128).
Note:
The matching address is always going to be
location
“
0
”
in a four-entry page for 288-bit search
(two LSBs of the matching index will be '00').
The SEARCH command is a pipelined operation
and executes a search at one-fourth the rate of the
frequency of CLK2X for 288-bit searches in x288-
configured tables. The latency of SADR, CE_L,
ALE_L, WE_L, SSV, and SSF from the 288-bit
SEARCH command (measured in CLK cycles)
from the CLK2X cycle that contains Cycles C and
D shown in Table 48, page 117.
The latency of a SEARCH from command to
SRAM access cycle is 6 for only a single device in
the table and TLSZ = 10. In addition, SSV and SSF
shift further to the right for different values of
HLAT, as specified in Table 49, page 117
The 288-bit SEARCH operation is pipelined and
executes as follows:
–
Four cycles from the last cycle of the SEARCH
command each of the devices knows the out-
come internal to it for that operation.
–
In the fifth cycle from the SEARCH command,
the devices in a block (which is less than or
equal to eight devices resolving the winner with-
in them using an LHI[6:0] and LHO[1:0] signal-
ling mechanism) arbitrate for a winner.
–
In the sixth cycle after the SEARCH command,
the blocks of devices resolve the winning block
through a BHI[2:0] and BHO[2:0] signalling
mechanism. The winning device within the win-
ning block is the global winning device for the
SEARCH operation.
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