參數(shù)資料
型號(hào): M74HCT648B1R
廠(chǎng)商: 意法半導(dǎo)體
元件分類(lèi): 通用總線(xiàn)功能
英文描述: HCT646 OCTAL BUS TRANSCEIVER/REGISTER 3-STATE HCT648 OCTAL BUS TRANSCEIVER/REGISTER 3-STATE, INV.
中文描述: HCT646八路總線(xiàn)收發(fā)器/注冊(cè)3態(tài)HCT648八路總線(xiàn)收發(fā)器/注冊(cè)三態(tài),刑事調(diào)查。
文件頁(yè)數(shù): 1/12頁(yè)
文件大小: 201K
代理商: M74HCT648B1R
M74HCT646
M74HCT648
October 1993
HCT648 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE,INV.)
.
HIGH SPEED
f
MAX
= 60 MHz (TYP.) AT V
CC
= 5 V
.
LOWPOWER DISSIPATION
I
CC
= 4
μ
A(MAX.) AT T
A
= 25
°
C
.
COMPATIBLE WITHTTL OUTPUTS
V
IH
= 2V (MIN.) V
IL
= 0.8V (MAX)
.
OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
I
OH
= I
OL
= 6 mA (MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
PIN ANDFUNCTION COMPATIBLE
WITH 54/74LS646/648
HCT646 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE)
B1R
(Plastic Package)
ORDER CODES :
M74HCTXXXM1R
M74HCTXXXB1R
M1R
(Micro Package)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN CONNECTIONS
(top view)
GAB, GAB, CAB,
SAB,SBA, CBA
A, B
DESCRIPTION
The M74HCT646/648 are high speed CMOS
OCTALBUS TRANSCEIVERS AND REGISTERS,
(3-STATE) fabricated in silicon gate C
2
MOS tech-
nology.
They
have
the
performance of LSTTL combined with true CMOS
low power consumption. These devices consist of
bus transceiver circuits with 3-state output, D-type
flip-flops, and control circuitry arranged for multi-
plexed transmission of data directly from the input
bus or from the internal registers. Data on the A or
B bus will be clocked into the registers on the low-
to-high transition of theappropriate clock pin (Clock
AB - or Clock BA). Enable (G) and direction (DIR)
pinsare provided tocontrol thetransceiverfunction-
s. In the transceiver mode, data present at the
high-impedance port maybestoredineitherregister
or in both. The selectcontrols (Select ABselect BA)
can multiplex stored and real-time (transparent
mode)data. The direction control determines which
bus will receive data when enable G is active (low).
In theisolation mode (enable G high), ”A” data may
be stored in one register and/or ”B” data may be
storedinthe other register. When anoutput function
is disabled, the input function is still enabled and
may be used to store and transmit data. Only one
of the two buses, A or B, may be driven at a time.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.This integrated circuit has input and output
characteristics that are fully compatible with 54/74
LSTTL logic families. M74HCT devices are de-
signedto directly interface HSC
2
MOS systems with
TTL and NMOScomponents. They are also plug in
replacements for LSTTL devices giving a reduction
of power consumption.
same
high
speed
1/12
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