- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄180240 > M7A3P400-FFG256 FPGA, 400000 GATES, 350 MHz, PBGA256 PDF資料下載
參數(shù)資料
| 型號(hào)： | M7A3P400-FFG256 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 400000 GATES, 350 MHz, PBGA256 |
| 封裝： | 1 MM PITCH, FBGA-256 |
| 文件頁數(shù)： | 13/246頁 |
| 文件大?。?/td> | 3010K |
| 代理商： | M7A3P400-FFG256 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當(dāng)前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁
ProASIC3/E Flash Family FPGAs
v2.1
1-5
In addition, every SRAM block has an embedded FIFO
control unit. The control unit allows the SRAM block to
be configured as a synchronous FIFO without using
additional core VersaTiles. The FIFO width and depth are
programmable. The FIFO also features programmable
Almost Empty (AEMPTY) and Almost Full (AFULL) flags in
addition to the normal Empty and Full flags. The
embedded FIFO control unit contains the counters
necessary for generation of the read and write address
pointers. The embedded SRAM/FIFO blocks can be
cascaded to create larger configurations.
PLL and CCC
ProASIC3 devices provide designers with very flexible
clock conditioning capabilities. Each member of the
ProASIC3 family contains six CCCs. One CCC (center west
side) has a PLL. The A3P030 does not have a PLL.
The six CCC blocks are located at the four corners and the
centers of the east and west sides.
All six CCC blocks are usable; the four corner CCCs and
the east CCC allow simple clock delay operations as well
as clock spine access.
The inputs of the six CCC blocks are accessible from the
FPGA core or from one of several inputs located near the
CCC that have dedicated connections to the CCC block.
The CCC block has these key features:
Wide input frequency range (fIN_CCC) = 1.5 MHz to
350 MHz
Output frequency range (fOUT_CCC) = 0.75 MHz to
350 MHz
Clock delay adjustment via programmable and
fixed delays from –7.56 ns to +11.12 ns
2 programmable delay types for clock skew
minimization
Clock frequency synthesis (for PLL only)
Additional CCC specifications:
Internal phase shift = 0°, 90°, 180°, and 270°.
Output phase shift depends on the output divider
configuration (for PLL only).
Output duty cycle = 50% ± 1.5% or better (for PLL
only)
Low output jitter: worst case < 2.5% × clock period
peak-to-peak period jitter when single global
network used (for PLL only)
Maximum acquisition time = 300 s (for PLL only)
Low power consumption of 5 mW
Exceptional tolerance to input period jitter—
allowable input jitter is up to 1.5 ns (for PLL only)
Four
precise
phases;
maximum
misalignment
between adjacent phases of 40 ps × (350 MHz /
fOUT_CCC) (for PLL only)Global Clocking
ProASIC3 devices have extensive support for multiple
clocking domains. In addition to the CCC and PLL support
described above, there is a comprehensive global clock
distribution network.
Each VersaTile input and output port has access to nine
VersaNets: six chip (main) and three quadrant global
networks. The VersaNets can be driven by the CCC or
directly accessed from the core via multiplexers (MUXes).
The VersaNets can be used to distribute low-skew clock
signals or for rapid distribution of high fanout nets.
I/Os with Advanced I/O Standards
The ProASIC3 family of FPGAs features a flexible I/O
structure, supporting a range of voltages (1.5 V, 1.8 V,
2.5 V, and 3.3 V). ProASIC3 FPGAs support many different
I/O standards—single-ended and differential.
The I/Os are organized into banks, with two or four
banks per device. The configuration of these banks
determines the I/O standards supported.
Each I/O module contains several input, output, and
enable
registers.
These
registers
allow
the
implementation of the following:
Single-Data-Rate applications
Double-Data-Rate applications—DDR LVDS, BLVDS,
and M-LVDS I/Os for point-to-point communications
ProASIC3 banks for the A3P250 device and above
support LVPECL, LVDS, BLVDS and M-LVDS. BLVDS and M-
LVDS can support up to 20 loads.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M7A3P400-FFG484 | FPGA, 400000 GATES, 350 MHz, PBGA484 |
| M7A3P400-FFGG144 | FPGA, 400000 GATES, 350 MHz, PBGA144 |
| M7A3P400-FFGG256 | FPGA, 400000 GATES, 350 MHz, PBGA256 |
| M7A3P400-FFGG484 | FPGA, 400000 GATES, 350 MHz, PBGA484 |
| M7A3P400-FG144I | FPGA, 400000 GATES, 350 MHz, PBGA144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M7A5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7A9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7AFS600-1FG256 | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
| M7AFS600-1FG256ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M7AFS600-1FG256I | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。