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| 型號(hào)： | M7A3P400-FPQG208 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 400000 GATES, 350 MHz, PQFP208 |
| 封裝： | 0.50 MM PITCH, GREEN, PLASTIC, QFP-208 |
| 文件頁(yè)數(shù)： | 209/246頁(yè) |
| 文件大?。?/td> | 3010K |
| 代理商： | M7A3P400-FPQG208 |
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ProASIC3/E Flash Family FPGAs
v2.1
2-53
from programming to operating mode, the I/Os are
instantly configured to the desired user configuration.
Unused I/Os are configured as follows:
Output buffer is disabled (with tristate value of high
impedance)
Input buffer is disabled (with tristate value of high
impedance)
Weak pull-up is programmed
GL
Globals
GL I/Os have access to certain clock conditioning circuitry
(and the PLL) and/or have direct access to the global
network (spines). Additionally, the global I/Os can be
used as I/Os, since they have identical capabilities.
Unused GL pins are configured as inputs with pull-up
resistors. See more detailed descriptions of global I/O
connectivity in the "Clock Conditioning Circuits" section
on page 2-15. All inputs labeled GC/GF are direct inputs
into the quadrant clocks. For example, if GAA0 is used
for an input, GAA1 and GAA2 are no longer available for
input to the quadrant globals. All inputs labeled GC/GF
are direct input into the chip level globals and the rest
are connected to the quadrant globals. The inputs to the
global network are multiplexed and only one input can
be used as a global input.
Refer to the "User I/O Naming Convention" section on
page 2-50 for a explanation of the naming of global
pins.
JTAG Pins
ProASIC3 devices have a separate bank for the dedicated
JTAG pins. The JTAG pins can be run at any voltage from
1.5 V to 3.3 V (nominal). VCC must also be powered for
the JTAG state machine to operate, even if the device is
in bypass mode; VJTAG alone is insufficient. Both VJTAG
and VCC to the ProASIC3 part must be supplied to allow
JTAG signals to transition the ProASIC3 device. Isolating
the JTAG power supply in a separate I/O bank gives
greater flexibility in supply selection and simplifies
power supply and PCB design. If the JTAG interface is
neither used nor planned for use, the VJTAG pin together
with the TRST pin could be tied to GND.
TCK
Test Clock
Test clock input for JTAG boundary scan, ISP, and UJTAG.
The TCK pin does not have an internal pull-up/down
resistor. If JTAG is not used, Actel recommends tying off
TCK to GND through a resistor placed close to the FPGA
pin. This prevents JTAG operation in case TMS enters an
undesired state.
Note that to operate at all VJTAG voltages, 500 Ω to 1 kΩ
will satisfy the requirements. Refer to Table 2-24 for
more information.
TDI
Test Data Input
Serial input for JTAG boundary scan, ISP, and UJTAG
usage. There is an internal weak pull-up resistor on the
TDI pin.
TDO
Test Data Output
Serial output for JTAG boundary scan, ISP, and UJTAG
usage.
TMS
Test Mode Select
The TMS pin controls the use of the IEEE1532 boundary
scan pins (TCK, TDI, TDO, TRST). There is an internal weak
pull-up resistor on the TMS pin.
TRST
Boundary Scan Reset Pin
The TRST pin functions as an active low input to
asynchronously initialize (or reset) the boundary scan
circuitry. There is an internal weak pull-up resistor on the
TRST pin. If JTAG is not used, an external pull-down
resistor could be included to ensure the test access port
(TAP) is held in reset mode. The resistor values must be
chosen from Table 2-24 and must satisfy the parallel
resistance value requirement. The values in Table 2-24
correspond to the resistor recommended when a single
device is used and the equivalent parallel resistor when
multiple devices are connected via a JTAG chain.
In critical applications, an upset in the JTAG circuit could
allow entering an undesired JTAG state. In such cases,
Actel recommends tying off TRST to GND through a
resistor placed close to the FPGA pin.
Note that to operate at all VJTAG voltages, 500 Ω to 1 kΩ
will satisfy the requirements.
Special Function Pins
NC
No Connect
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
DC
Do Not Connect
This pin should not be connected to any signals on the
PCB. These pins should be left unconnected.
Table 2-24 Recommended Tie-Off Values for the TCK and
TRST Pins
VJTAG
Tie-Off Resistance
VJTAG at 3.3 V
200
Ω to 1 kΩ
VJTAG at 2.5 V
200
Ω to 1 kΩ
VJTAG at 1.8 V
500
Ω to 1 kΩ
VJTAG at 1.5 V
500
Ω to 1 kΩ
Notes:
1. Equivalent parallel resistance if more than one device is on
the JTAG chain.
2. The TCK pin can be pulled up/down.
3. The TRST pin be pulled down.
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