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| 型號： | M7A3P400-FPQG208 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 400000 GATES, 350 MHz, PQFP208 |
| 封裝： | 0.50 MM PITCH, GREEN, PLASTIC, QFP-208 |
| 文件頁數(shù)： | 210/246頁 |
| 文件大?。?/td> | 3010K |
| 代理商： | M7A3P400-FPQG208 |
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ProASIC3/E Flash Family FPGAs
2- 54
v2.1
Software Tools
Overview of Tools Flow
The ProASIC3 family of FPGAs is fully supported by both
Actel Libero IDE and Designer FPGA development
software. Actel Libero IDE is an integrated design
manager that seamlessly integrates design tools while
guiding the user through the design flow, managing all
design and log files and passing necessary design data
among tools. Additionally, Libero IDE allows users to
integrate both schematic and HDL synthesis into a single
flow and verify the entire design in a single environment
(see the Libero IDE flow diagram located on the Actel
website).
Libero
IDE
includes
Synplify
AE
from
Synplicity, ViewDraw AE from Mentor Graphics,
ModelSim HDL Simulator from Mentor Graphics,
WaveFormer LiteTM AE from SynaptiCAD, PALACETM AE
Physical Synthesis from Magma Design Automation,TM
and Designer software from Actel.
Actel Designer software is a place-and-route tool and
provides a comprehensive suite of backend support tools
for FPGA development. The Designer software includes
the following:
Timer—a world-class integrated static timing
analyzer and constraints editor that supports
timing-driven place-and-route
NetlistViewer—a design netlist schematic viewer
ChipPlanner—a graphical floorplanner viewer and
editor
SmartPower—a tool that enables the designer to
quickly estimate the power consumption of a
design
PinEditor—a graphical application for editing pin
assignments and I/O attributes
I/O Attribute Editor—a tool that displays all
assigned and unassigned I/O macros and their
attributes in a spreadsheet format
With the Designer software, a user can lock the design
pins before layout while minimally impacting the results
of place-and-route. Additionally, Actel back-annotation
flow is compatible with all the major simulators. Another
tool included in the Designer software is the SmartGen
core generator, which easily creates popular and
commonly used logic functions for implementation into
your schematic or HDL design.
Actel Designer software is compatible with the most
popular FPGA design entry and verification tools from
EDA vendors such as Mentor Graphics, Synplicity,
Synopsys, and Cadence. The Designer software is
available for both the Windows and UNIX operating
systems.
Programming
Programming can be performed using tools such as
Silicon Sculptor II (BP Micro Systems) or FlashPro3 (Actel).
The user can generate STP programming files from the
Designer software and use these files to program a
device.
ProASIC3 devices can be programmed in system. For
more information on ISP of ProASIC3 devices, refer to the
Microprocessor application notes.
The ProASIC3 device can be serialized with a unique
identifier stored in the FlashROM of each device.
Serialization is an automatic assignment of serial
numbers that are stored within the STAPL file used for
programming. The area of the FlashROM used for
holding such identifiers is defined using SmartGen, and
the range of serial numbers to be used is defined at the
time of STAPL file generation with FlashPoint. Serial
number values for STAPL file generation can even be
read from a file of predefined values. Serialized
programming using a serialized STAPL file can be done
through Actel In-House Programming (IHP), an external
vendor using Silicon Sculptor software, or the ISP
capabilities of the FlashPro software.
Security
ProASIC3 devices have a built-in 128-bit AES decryption
core (except the A3P030 device). The decryption core
facilitates secure in-system programming of the FPGA
core array fabric and the FlashROM. The FlashROM and
the FPGA core fabric can be programmed independently
from each other, allowing the FlashROM to be updated
without the need for change to the FPGA core fabric.
The AES master key is stored in on-chip nonvolatile
memory (Flash). The AES master key can be preloaded
into parts in a secure programming environment (such as
the Actel in-house programming center), and then
"blank"
parts
can
be
shipped
to
an
untrusted
programming
or
manufacturing
center
for
final
personalization with an AES-encrypted bitstream. Late-
stage product changes or personalization can be
implemented easily and securely by simply sending a
STAPL file with AES encrypted data. Secure remote field
updates over public networks (such as the Internet) are
possible by sending and programming a STAPL file with
AES-encrypted data.
128-Bit AES Decryption8
The 128-bit AES standard (FIPS-192) block cipher is the
NIST (National Institute of Standards and Technology)
replacement
for
DES
(Data
Encryption
Standard
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M7A3P400-PQ208I | FPGA, 400000 GATES, 350 MHz, PQFP208 |
| M7A3P400-PQ208 | FPGA, 400000 GATES, 350 MHz, PQFP208 |
| M7A3P400-PQG208I | FPGA, 400000 GATES, 350 MHz, PQFP208 |
| M7A3P400-PQG208 | FPGA, 400000 GATES, 350 MHz, PQFP208 |
| M7A3P600-1FG144I | FPGA, 600000 GATES, 350 MHz, PBGA144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M7A5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7A9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7AFS600-1FG256 | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
| M7AFS600-1FG256ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M7AFS600-1FG256I | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
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