參數(shù)資料
型號(hào): M93S56-WBN3TG
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: 4Kbit, 2Kbit and 1Kbit 16-bit wide MICROWIRE Serial Access EEPROM with Block Protection
中文描述: 4Kbit,2Kbit和1Kbit 16位寬MICROWIRE串行EEPROM的訪問與街區(qū)保護(hù)
文件頁數(shù): 25/34頁
文件大?。?/td> 525K
代理商: M93S56-WBN3TG
25/34
M93S66, M93S56, M93S46
Table 19. AC Characteristics (M93Sx6-R)
Note: 1. t
CHCL
+ t
CLCH
1 / f
C
.
2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
3. Preliminary Data: this product is under development. For more infomation, please contact your nearest ST sales office.
Test conditions specified in
Table 9.
and
Table 7.
Symbol
Alt.
Parameter
Min.
3
Max.
3
Unit
f
C
f
SK
Clock Frequency
D.C.
1
MHz
t
PRVCH
t
PRES
Protect Enable Valid to Clock High
50
ns
t
WVCH
t
PES
Write Enable Valid to Clock High
50
ns
t
CLPRX
t
PREH
Clock Low to Protect Enable Transition
0
ns
t
SLWX
t
PEH
Chip Select Low to Write Enable Transition
250
ns
t
SLCH
Chip Select Low to Clock High
250
ns
t
SHCH
t
CSS
Chip Select Set-up Time
50
ns
t
SLSH2
t
CS
Chip Select Low to Chip Select High
250
ns
t
CHCL1
t
SKH
Clock High Time
250
ns
t
CLCH1
t
SKL
Clock Low Time
250
ns
t
DVCH
t
DIS
Data In Set-up Time
100
ns
t
CHDX
t
DIH
Data In Hold Time
100
ns
t
CLSH
t
SKS
Clock Set-up Time (relative to S)
100
ns
t
CLSL
t
CSH
Chip Select Hold Time
0
ns
t
SHQV
t
SV
Chip Select to Ready/Busy Status
400
ns
t
SLQZ
t
DF
Chip Select Low to Output Hi-Z
200
ns
t
CHQL
t
PD0
Delay to Output Low
400
ns
t
CHQV
t
PD1
Delay to Output Valid
400
ns
t
W
t
WP
Erase/Write Cycle time
10
ms
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