參數(shù)資料
型號(hào)： M95010
廠商： 意法半導(dǎo)體
元件分類： DRAM
英文描述： 1K Serial SPI EEPROM with High Speed Clock and Positive Clock Strobe(帶高速時(shí)鐘和正向時(shí)鐘選通的1K串聯(lián)SPI EEPROM)
中文描述： 一千串行SPI EEPROM，帶有高速時(shí)鐘和積極的時(shí)鐘選通（帶高速時(shí)鐘和正向時(shí)鐘選通的一千串聯(lián)的SPI EEPROM的）
文件頁(yè)數(shù)： 6/20頁(yè)
文件大?。?/td> 151K
代理商： M95010
Write Status Register (WRSR)
The WRSR instruction writes (only) the BP1 and
BP0 bits allowing to define the size of protected
memory. The user may read the blocks but will be
unable to write within the protected blocks. The
blocks and respective WRSR control bits are
shown in Table 4.
When the WRSR instruction and the 8 bits of the
Status Register are latched-in, the internal write
cycle is then triggered by the rising edge of S.
This rising edge of S must appear no later than the
16th clock cycle of the WRSR instruction of the
Status Register content (it must not appear a 17th
clock pulse before the rising edge of S), otherwise
the internal write sequence is not performed.
Read Operation
The chip is first selected by putting S low. The serial
one byte read instruction is followed by a one byte
address (A7-A0), each bit being latched-in during
the rising edge of the clock (C). Bit 3 (see Table 3)
of the read instruction contains address bit A8
(most significant address bit). Then the data stored
in the memory at the selected address is shifted out
on the Q output pin; each bit being shifted out
during the falling edge of the clock (C).
The data stored in the memory at the next address
can be read in sequence by continuing to provide
clock pulses. The byte address is automatically
incremented to the next higher address after each
byte of data is shifted out. When the highest ad-
dress is reached, the address counter rolls over to
0h allowing the read cycle to be continued indefi-
nitely. The read operation is terminated by dese-
lecting the chip. The chip can be deselected at any
time during data output. Any read attempt during a
write cycle will be rejected and will deselect the
chip.
C
D
AI01440
S
Q
A7
2
1
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
A6 A5 A4 A3 A2 A1 A0
A8
20 21 22 23
7
6
5
4
3
2
0
1
HIGH IMPEDANCE
DATA OUT
INSTRUCTION
BYTE ADDRESS
0
Figure 6. Read Operation Sequence
Status Register Bits
Protected Block
Array Address Protected
BP1
BP0
M95040
M95020
M95010
0
0
none
none
none
none
0
1
Upper quarter
180h - 1FFh
C0h - FFh
60h - 7Fh
1
0
Upper half
100h - 1FFh
80h - FFh
40h - 7Fh
1
1
Whole memory
000h - 1FFh
00h - FFh
00h - 7Fh
Table 4. Write Protected Block Size
Notes:
A8 = A7 = X on M95010 and M95020; A8 is only active on M95040.
X = Don’t care.
6/20
M95040, M95020, M95010
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M95010BN 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock
M95010-BN3 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock
M95010-BN3/W 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock
M95010-BN3G 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock
M95010-BN3G/W 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock
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