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參數資料
| 型號： | M95010 |
| 廠商： | 意法半導體 |
| 元件分類： | DRAM |
| 英文描述： | 1K Serial SPI EEPROM with High Speed Clock and Positive Clock Strobe(帶高速時鐘和正向時鐘選通的1K串聯SPI EEPROM) |
| 中文描述： | 一千串行SPI EEPROM，帶有高速時鐘和積極的時鐘選通（帶高速時鐘和正向時鐘選通的一千串聯的SPI EEPROM的） |
| 文件頁數： | 9/20頁 |
| 文件大?。?/td> | 151K |
| 代理商： | M95010 |
Byte Write Operation
Prior to any write attempt, the write enable latch
must be set by issuing the WREN instruction. First
the device is selected (S = low) and a serial WREN
instruction byte is issued. Then the product is de-
selected by taking S high. After the WREN instruc-
tion byte is sent, the Memory will set the write
enable latch and then remain in standby until it is
deselected. Then the write state is entered by
selecting the chip, issuing two bytes of instruction
and address, and one byte of data.
Chip Select (S) must remain low for the entire
duration of the operation. The product must be
deselected just after the eighth bit of data has been
latched in. If not, the write process is cancelled. As
soon as the product is deselected, the self-timed
write cycle is initiated. While the write is in progress,
the status register may be read to check BP1, BP0,
WEL and WIP. WIP is high during the self-timed
write cycle. When the cycle is completed, the write
enable latch is reset.
Page Write Operation
A maximum of 16 bytes of data may be written
during one non-volatile write cycle. All 16 bytes
must reside on the same page. The page write
mode is the same as the byte write mode except
that instead of deselecting the device after the first
byte of data, up to 15 additional bytes can be shifted
in prior to deselecting the chip. A page address
begins with address xxxx 0000 and ends with xxxx
1111. If the address counter reaches xxxx 1111 and
the clock continues, the counter will roll over to the
first address of the page (xxxx 0000) and overwrite
any previously written data. The programming cy-
cle will only start if the S transition occurs just after
the eighth bit of data of a word is received.
POWER ON STATE
After a Power up the Memory is in the following
state:
– The device is in the low power standby state.
– The chip is deselected.
– The chip is not in hold condition.
The Status Register content at power-up is:
BP1
BP0
WEL
WIP
1
1
1
1
0
0
0
0
C
D
AI01445
S
Q
2
1
3
4
5
6
7
8
9 10 11 12 13 14 15
HIGH IMPEDANCE
INSTRUCTION
STATUS REG.
0
Figure 11. WRSR: Write Status Register Sequence
9/20
M95040, M95020, M95010
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相關代理商/技術參數 |
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|---|---|
| M95010BN | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95010-BN3 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95010-BN3/W | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95010-BN3G | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95010-BN3G/W | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
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