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參數(shù)資料
| 型號(hào)： | MAC7111CPV50 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 50 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 0.50 MM PITCH, LQFP-144 |
| 文件頁(yè)數(shù)： | 13/48頁(yè) |
| 文件大?。?/td> | 1282K |
| 代理商： | MAC7111CPV50 |
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20
MAC7100 Microcontroller Family Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical Characteristics
3.9.1
Read and Write Bus Cycles
Table 23 lists processor bus output timings. Read/write bus timings listed in Table 23 are shown in Figure 7
and Figure 8.
Table 23. External Bus Output Timing Specifications
Num
C
Rating
Symbol
Min
Max
Unit
Control Outputs
L6a
CLKOUT high to chip selects valid 1
1
CSn transitions after the falling edge of CLKOUT.
tCHCV
—0.5tCYC + 10
ns
L6b
CLKOUT high to byte select (BS[1:0]) valid 2
2
BSn transitions after the falling edge of CLKOUT.
tCHBV
—0.5tCYC + 10
ns
L6c
CLKOUT high to output select (OE) valid 3
3
OE transitions after the falling edge of CLKOUT.
tCHOV
—0.5tCYC + 10
ns
L7a
CLKOUT high to control output (BS[1:0], OE) invalid
tCHCOI 0.5tCYC + 2
—
ns
L7b
CLKOUT high to chip selects invalid
tCHCI
0.5tCYC + 2
—
ns
Address and Attribute Outputs
L8
CLKOUT high to address (ADDR[21:0]) and control
(R/W) valid
tCHAV
—10
ns
L9
CLKOUT high to address (ADDR[21:0]) and control
(R/W) invalid
tCHAI
2—
ns
Data Outputs
L10
CLKOUT high to data output (DATA[15:0]) valid
tCHDOV
—13
ns
L11
CLKOUT high to data output (DATA[15:0]) invalid
tCHDOI
2—
ns
L12
CLKOUT high to data output (DATA[15:0]) high impedance
tCHDOZ
—9
ns
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