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參數(shù)資料
| 型號： | MAC7111CPV50 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 50 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 0.50 MM PITCH, LQFP-144 |
| 文件頁數(shù)： | 9/48頁 |
| 文件大?。?/td> | 1282K |
| 代理商： | MAC7111CPV50 |
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17
MAC7100 Microcontroller Family Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical Characteristics
3.8.3
PLL Characteristics
3.8.4
Crystal Monitor Time-out
The time-out Table 19 shows the delay for the crystal monitor to trigger when the clock stops, either at the high
or at the low level. The corresponding clock period with an ideal 50% duty cycle is twice this time-out value.
3.8.5
Clock Quality Checker
The timing for the clock quality check is derived from the oscillator and the VCO frequency range in
Table 18. These numbers define the upper time limit for the individual check windows to complete.
Table 18. PLL Characteristics
Num C
Rating
Symbol
Min
Typ
Max
Unit
J1
PLL reference frequency, crystal oscillator range 1
1 VDDPLL at 2.5 V.
fREF
0.5
—
16
MHz
J2
P Self Clock Mode frequency
fSCM
1—
5.5
MHz
J3
D VCO locking range
fVCO
8—
40
MHz
J4
D Lock Detector transition from Acquisition to Tracking mode
|trk|
3—4
% 2
2 Percentage deviation from target frequency
J5
D Lock Detection
|Lock|
0—
1.5
% 2
J6
D Un-Lock Detection
|unl|
0.5
—
2.5
% 2
J7
D Lock Detector transition from Tracking to Acquisition mode
|unt|
6—8
% 2
J8
C PLLON Total Stabilization delay (Auto Mode) 3
3 PLL stabilization delay is highly dependent on operational requirement and external component values (for
example, crystal and XFC filter component values). Notes 4 and 5 show component values for a typical
configurations. Appropriate XFC filter values should be chosen based on operational requirement of system.
tstab
—0.5 4
4 fREF = 4 MHz, fSYS = 25 MHz (REFDV = 0x03, SYNR = 0x01), CS = 4.7 nF, CP = 470 pF, RS =10 K.
3 5
5 fREF = 4 MHz, fSYS = 8 MHz (REFDV = 0x00, SYNR = 0x01), CS = 33 nF, CP = 3.3 nF, RS = 2.7 K.
ms
J9
D PLLON Acquisition mode stabilization delay 3
tacq
—0.3 5
1 4
ms
J10 D PLLON Tracking mode stabilization delay 3
tal
—0.2 5
2 4
ms
J11 D Charge pump current acquisition mode
| ich |
—
38.5
—
A
J12 D Charge pump current tracking mode
| ich |
—3.5
—
A
J13 D Jitter fit VCO loop gain parameter
K1
—
–100
—
MHz/V
J14 D Jitter fit VCO loop frequency parameter
f1
—60—
MHz
J15 C Jitter fit parameter 1
j1
——
TBD
% 4
J16 C Jitter fit parameter 2
j2
——
TBD
% 4
Table 19. Crystal Monitor Time-Outs
Min
Typ
Max
Unit
610
18.5
s
Table 20. CRG Maximum Clock Quality Check Timings
Clock Check Windows
Value
Unit
Check Window
9.1 to 20.0
ms
Timeout Window
0.46 to 1.0
s
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