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參數(shù)資料
| 型號： | MAC7111MAG40 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 11/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT FLASH 144-LQFP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | MAC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 32-位 |
| 速度： | 40MHz |
| 連通性： | CAN，EBI/EMI，I²C，SCI，SPI |
| 外圍設(shè)備： | DMA，POR |
| 輸入/輸出數(shù)： | 112 |
| 程序存儲器容量： | 544KB（544K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.35 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x8/10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 144-LQFP |
| 包裝： | 托盤 |
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ElectricalCharacteristics
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Freescale Semiconductor
19
3.8.6
Startup
Table 23 summarizes several startup characteristics. Refer to Section 4.3.6.10, “CRG Operating Mode
Details,” in the MAC7100 Microcontroller Family Reference Manual (MAC7100RM) for details.
3.8.6.1
Power On and Low Voltage Reset (POR and LVR)
The VPORR and VPORA levels are derived from VDD2.5. The VLVRA level is derived from VDD2.5. They
are also valid if the device is powered externally. After releasing a POR or LVR reset, the oscillator and
clock quality checks start. After tCQOUT (Table 19, J4) if no valid oscillation is detected, the MCU will
start using the internal self-generated clock. The minimum startup time is given by tuposc (Table 19, J3).
3.8.6.2
SRAM Data Retention
SRAM content integrity is guaranteed if the CRGFLG[PORF] bit is not set following a reset operation.
3.8.6.3
External Reset
When external reset is asserted for a time greater than PWRSTL, the CRG generates an internal reset and
the CPU fetches the reset vector without a clock quality check, if there was stable oscillation before reset.
3.8.6.4
Stop Recovery
The MCU can return from stop to run mode in response to an external interrupt or an API. Two delays
occur before the MCU resumes execution. First, the voltage regulator must exit reduced power mode and
return to full performance mode (this assumes that the internal regulator is used rather than driving VDD2.5
and VDDPLL with an external regulator). Second, a clock quality check is performed in the same manner
as for a power-on reset before releasing the clocks to the system.
3.8.6.5
Pseudo Stop Recovery
Recovery from pseudo stop mode is similar to stop mode in that the VREG must return to FPM, but since
the oscillator is not stopped there is no delay for clock stabilization. The MCU is returned to run mode by
internal or external interrupts.
3.8.6.6
Doze Recovery
Recovery from doze mode avoids both the VREG and oscillator recovery periods. The MCU is returned
to run mode by internal or external interrupts.
Table 23. CRG Startup Characteristics
Num C
Rating
Symbol
Min
Typ
Max
Unit
L1
D Reset input pulse width
PWRSTL
2—
—
tOSC
L2
D Startup from Reset
nRST
192
—
196
tOSC
L3
D XIRQ, IRQ pulse width, edge-sensitive mode
PWIRQ
20
—
ns
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