參數(shù)資料
型號: MAC7111MAG40
廠商: Freescale Semiconductor
文件頁數(shù): 6/56頁
文件大?。?/td> 0K
描述: IC MCU 32BIT FLASH 144-LQFP
標準包裝: 60
系列: MAC7xxx
核心處理器: ARM7
芯體尺寸: 32-位
速度: 40MHz
連通性: CAN,EBI/EMI,I²C,SCI,SPI
外圍設備: DMA,POR
輸入/輸出數(shù): 112
程序存儲器容量: 544KB(544K x 8)
程序存儲器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 2.35 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 16x8/10b
振蕩器型: 內部
工作溫度: -40°C ~ 125°C
封裝/外殼: 144-LQFP
包裝: 托盤
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Electrical Characteristics
Freescale Semiconductor
14
3.7.5
Chip Power Up and Voltage Drops
The VREG sub-modules LVI (low voltage interrupt), POR (power on reset) and LVR (low voltage reset)
handle chip power-up or drops of the supply voltage. Refer to Figure 2.
Figure 2. VREG Chip Power-up and Voltage Monitoring
3.7.6
Output Loads
The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits. No external
DC load is allowed. Capacitive loads are specified in Table 18. Capacitors with X7R dielectricum are
required.
Table 18. VREG Recommended Load Capacitances
Rating
Symbol
Min
Typ
Max
Unit
Load Capacitance per VDD2.5 pin
1
NOTES:
1. Refer to Table 38 for the specific number of VDD2.5 pins on various packages. Each VDD2.5 pin should have the
recommended loading as described in Section 3.7.3, “Circuit Board Layout,of the MAC7100 Microcontroller Family
Reference Manual (MAC7100RM).
CLVDD
200
220
12000
nF
Load Capacitance on VDDPLL pin
CLVDDfcPLL
90
220
5000
nF
LVI Disabled
due to LVR
VLVID
VLVRD
LVR
POR
LVI
VPORD
VLVRA
VLVIA
Time
LVI Enabled
VDDA
VDD2.5
Voltage
Note: Not to scale.
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