參數(shù)資料
型號： MAC7111MAG40
廠商： Freescale Semiconductor
文件頁數(shù)： 7/56頁
文件大?。?/td> 0K
描述： IC MCU 32BIT FLASH 144-LQFP
標準包裝： 60
系列： MAC7xxx
核心處理器： ARM7
芯體尺寸： 32-位
速度： 40MHz
連通性： CAN，EBI/EMI，I²C，SCI，SPI
外圍設備： DMA，POR
輸入/輸出數(shù)： 112
程序存儲器容量： 544KB（544K x 8）
程序存儲器類型： 閃存
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 2.35 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x8/10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 144-LQFP
包裝： 托盤
ElectricalCharacteristics
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Freescale Semiconductor
15
3.8
Clock and Reset Generator
This section describes the electrical characteristics for the oscillator, phase-locked loop, clock monitor and
reset generator.
3.8.1
Oscillator Characteristics
The MAC7100 Family features an internal low power loop controlled Pierce oscillator and a full swing
Pierce oscillator/external clock mode. The selection of loop controlled Pierce oscillator or full swing
Pierce oscillator/external clock depends on the level of the XCLKS signal at the rising edge of the RESET
signal. Before asserting the oscillator to the internal system clock distribution subsystem, the quality of the
oscillation is checked for each start from either power on, STOP or oscillator fail. tCQOUT specifies the
maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation
is not detected. The quality check also determines the minimum oscillator start-up time tUPOSC. The device
also features a clock monitor. A Clock Monitor Failure is asserted if the frequency of the incoming clock
signal is below the Clock Monitor Assert Frequency fCMFA.
Table 19. Oscillator Characteristics
Num C
Rating
Symbol
Min
Typ
Max
Unit
J1a
C Crystal oscillator range (loop controlled Pierce)
fOSC
1
NOTES:
1. If CLKSEL[PLLSEL] is clear then the system clock (fSYS) is equal to fOSC, otherwise it is equal to fVCO (table
Table 20, K3). Throughout this document, tSYS is used to specify a unit of time equal to 1 ÷ fSYS.
4.0
—
16
MHz
J1b
C Crystal oscillator range (full swing Pierce) 2 3
2. Depending on the crystal; a damping series resistor might be necessary
3. XCLKS asserted (low) during reset
0.5
—
40
MHz
J2
P Startup Current
IOSC
100
—
μA
J3
C Oscillator start-up time (loop controlled Pierce)
tUPOSC
—3 4
4. fOSC = 4 MHz, C = 22 pF (refer to the MAC7100 Microcontroller Family Reference Manual (MAC7100RM) for circuit
board layout recommendations, including oscillator capacitor placement and values).
50 5
5. Maximum value is for extreme cases using high Q, low frequency crystals
ms
J4
D Clock Quality check time-out
tCQOUT
0.45
—
2.5
s
J5
P Clock Monitor Failure Assert Frequency
fCMFA
50
100
200
KHz
J6
P External square wave input frequency 3
fEXT
0.5
—
50
MHz
J7
D External square wave pulse width low
tEXTL
9.5
—
ns
J8
D External square wave pulse width high
tEXTH
9.5
—
ns
J9
D External square wave rise time
tEXTR
——
1
ns
J10
D External square wave fall time
tEXTF
——
1
ns
J11
D Input Capacitance (EXTAL, XTAL pins)
CIN
—7
—
pF
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